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| ( doc no. hx8347 - b - ds ) HX8347-B 240rgb x 320 dot, 262k color, w ith internal gram, tft mobile single chip driver preliminary version 01 december, 2009 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/
-p.2- h imax confidential this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. december, 2009 1. general description.............................................................................................................................. 9 2. features ............................................................................................................................................... 10 2.1 display ............................................................................................................................................ 10 2.2 display module................................................................................................................................ 10 2.3 display control interface................................................................................................................. 10 2.4 input power ......................................................................................................................................11 2.5 miscellaneous ..................................................................................................................................11 3. block diagram..................................................................................................................................... 12 3.1 block diagram ................................................................................................................................. 12 3.2 pin description ................................................................................................................................ 13 3.3 pin assignment ............................................................................................................................... 15 3.4 pad coordinates............................................................................................................................. 16 3.5 bump size....................................................................................................................................... 22 3.6 alignment mark ............................................................................................................................... 23 4. interface ............................................................................................................................................... 24 4.1 system interface circuit.................................................................................................................. 25 4.1.1 parallel bus system interface ................................................................................................. 26 4.1.2 mcu data color coding.......................................................................................................... 29 4.1.3 serial bus system interface .................................................................................................... 41 4.1.3.1 3-wire serial interface................................................................................................... 41 4.1.3.2 4-wire serial interface................................................................................................... 43 4.1.3.3 3-wire serial interface................................................................................................... 44 4.2 vsync interface ............................................................................................................................... 48 5.3 rgb interface ............................................................................................................................... 51 5. functional description ....................................................................................................................... 56 5.1 display data gram mapping.......................................................................................................... 56 5.2 gram to display address mapping ................................................................................................ 57 5.3 window address function .............................................................................................................. 59 5.4 tearing effect output line .............................................................................................................. 60 5.4.1 tearing effect line modes ....................................................................................................... 60 5.4.2 tearing effect line timing ....................................................................................................... 62 5.4.3 example 1: mpu write is faster than panel read .................................................................. 63 5.4.4 example 2: mpu write is slower than panel read ................................................................. 64 5.5 internal oscillator ............................................................................................................................ 65 5.6 source driver................................................................................................................................... 65 5.7 gate driver ...................................................................................................................................... 65 5.8 scan mode setting .......................................................................................................................... 66 5.9 lcd power generation circuit........................................................................................................ 67 5.9.1 power supply circuit ............................................................................................................... 67 5.9.2 lcd power generation scheme ............................................................................................. 69 5.10 gamma characteristic correction function.................................................................................... 70 5.11 power on/off sequence ................................................................................................................. 80 5.12 input / output pin state ................................................................................................................... 84 5.12.1 output pins.............................................................................................................................. 84 5.12.2 input pins................................................................................................................................. 84 5.13 otp programing ............................................................................................................................. 85 5.13.1 otp table ................................................................................................................................ 85 5.13.2 otp programming flow............................................................................................................ 86 5.13.3 otp sequence ........................................................................................................................ 87 5.13.4 otp read flow ........................................................................................................................ 88 5.14 content adaptive brightness control (cabc) function................................................................... 89 HX8347-B 240rgb x 320 dot, 262k color, with internal g ram, tft mobile single chip driver list of contents december, 2009 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.3- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. 6 . command ............................................................................................................................................ 93 6.1 command set ................................................................................................................................. 94 6.2 index register ................................................................................................................................. 98 6.3 driver id code(r00h) ...................................................................................................................... 98 6.4 driver output control (r01h) .......................................................................................................... 98 6.5 driving control (r02h) .................................................................................................................. 100 6.6 entry mode (r03h)........................................................................................................................ 100 6.7 16 bits data mapping (r05h )........................................................................................................ 103 6.8 display control 1 (r07h)............................................................................................................... 104 6.9 display control 2 (r08h)............................................................................................................... 105 6.10 display control 3 (r09h)............................................................................................................... 106 6.11 display control 4 (r0ah) .............................................................................................................. 107 6.12 rgb interface control 1 (r0ch) ................................................................................................... 108 6.13 te output position (r0dh) ........................................................................................................... 109 6.14 rgb interface control 2 (r0fh) ................................................................................................... 109 6.15 power control 1 (r10h ) ................................................................................................................110 6.16 power control 2 (r11h)..................................................................................................................112 6.17 power control 3 (r12h) .................................................................................................................113 6.18 power control 4 (r13h) .................................................................................................................114 6.19 ram address set (r20h~r21h) ....................................................................................................114 6.20 ram data write/read (r22h ) .......................................................................................................115 6.21 power control 7 (r29h ) ................................................................................................................117 6.22 frame rate control (r2bh ) ...........................................................................................................118 6.23 gamma control register (r30h~r3dh)........................................................................................118 6.24 get scan lines (r45h)....................................................................................................................119 6.25 horizontal start (r50h)...................................................................................................................119 6.26 horizontal end (r51h ) .................................................................................................................119 6.27 vertical start (r52h ) ......................................................................................................................119 6.28 vertical end (r53h )......................................................................................................................119 6.29 gate scan start position (r60h)................................................................................................... 121 6.30 base image control (r61h ) ......................................................................................................... 123 6.31 spi read/write control (r66h)..................................................................................................... 123 6.32 vertical scroll control (r6ah) ....................................................................................................... 124 6.33 partial image 1 display position (r80h) ....................................................................................... 124 6.34 partial image 1 area (start line) (r81h)....................................................................................... 124 6.35 partial image 1 area (end line) (r82h)........................................................................................ 124 6.36 partial image 2 display position (r83h) ....................................................................................... 124 6.37 partial image 2 area (start line) (r84h)....................................................................................... 125 6.38 partial image 2 area (end line) (r85h)........................................................................................ 125 6.39 panel interface control 1 (r90h) .................................................................................................. 127 6.40 panel interface control 2 (r92h) .................................................................................................. 127 6.41 panel interface control 3 (r97h) .................................................................................................. 128 6.42 panel interface control 4 (r98h) .................................................................................................. 128 6.43 otp vcm status and enable (ra2h) ........................................................................................... 129 6.44 otp index and otp mask (ra3h) ............................................................................................... 129 6.45 otp programming function (ra4h)............................................................................................. 129 6.46 otp programming id key (ra5h) ................................................................................................ 130 6.47 write display brightness (rb1h) .................................................................................................. 130 6.48 read display brightness (rb2h) .................................................................................................. 130 6.49 write ctrl display value (rb3h) ................................................................................................ 130 6.50 read ctrl display value (rb4h) ................................................................................................ 130 6.51 write content adaptive brightness control value (rb5h) ............................................................ 130 6.52 read content adaptive brightness control value (rb6h) ............................................................ 130 6.53 write cabc minimum brightness (rbeh) .................................................................................... 130 6.54 read cabc minimum brightness (rbfh) .................................................................................... 131 HX8347-B 240rgb x 320 dot, 262k color, with internal g ram, tft mobile single chip driver list of contents december, 2009 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.4- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. 6 .55 cabc control 1 (rc7h) ................................................................................................................ 132 6.56 cabc control 2 (rc8h) ................................................................................................................ 132 6.57 id control (rdah~dch)................................................................................................................ 133 6.58 deep stand by control (re6h)....................................................................................................... 133 6.59 otp data (rf3h) .......................................................................................................................... 133 6.60 otp id cnt (rf4h)...................................................................................................................... 133 6.61 otp vcom cnt (rf5h) .............................................................................................................. 134 7. layout recommendation ................................................................................................................. 135 7.1 maximum layout resistance .......................................................................................................... 136 7.2 external components connection.................................................................................................. 137 8. electrical characteristic................................................................................................................... 138 8.1 absolute maximum ratings .......................................................................................................... 138 8.2 esd protection level .................................................................................................................... 138 8.3 dc characteristics ........................................................................................................................ 139 8.4 ac characteristics ........................................................................................................................ 141 8.4.1 parallel interface characteristics (8080-series mpu) ........................................................... 141 8.4.2 serial interface characteristics ............................................................................................. 143 8.4.3 rgb interface characteristics............................................................................................... 144 8.4.4 reset input timing ................................................................................................................ 146 9. ordering information ........................................................................................................................ 147 10. revision history................................................................................................................................ 147 HX8347-B 240rgb x 320 dot, 262k color, with internal g ram, tft mobile single chip driver list of contents december, 2009 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.5- h imax confidential this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. december, 2009 figure 4.1: register read/write timing in parallel bus system interface (for i80 series mpu) ............. 27 figure 4.2: gram read/write timing in parallel bus system interface (for i80 series mpu) ............... 28 figure 4.3: example of i80- system 18-bit parallel bus interface ........................................................... 31 figure 4.4: input data bus and gram data mapping in 18-bit bus system interface with 18 bit-data i nput (im3, im2, im1, im=1010 or 1000) ......................................................................... 31 figure 4.5: example of i80 system 16-bit parallel bus interface type i .................................................... 32 figure 4.6: example of i80 system 16-bit parallel bus interface type ii ................................................... 32 figure 4.7: input data bus and gram data mapping in 16-bit bus system interface with 16-bit-data..... 32 figure 4.8: input data bus and gram data mapping in 16-bit bus system interface with 18 bit-data ..... 33 figure 4.9: input data bus and gram data mapping in 16-bit bus system interface with 18(16+2) ....... 33 figure 4.10: input data bus and gram data mapping in 16-bit bus system interface with 16 bit-data33 figure 4.11: input data bus and gram data mapping in 16-bit bus system interface with 18(16+2)... 33 figure 4.12 input data bus and gram data mapping in 16-bit bus system interface with 18(2+16) b it-data input (tri = 1, dfm = 1 and im3, im2, im1, im0=0010)............................... 34 figure 4.13: example of i80 system 9-bit parallel bus interface type i .................................................... 35 figure 4.14: example of i80 system 9-bit parallel bus interface type ii ................................................... 35 figure 4.15: input data bus and gram data mapping in 9-bit bus system interface with 18-bit-data..... 36 figure 4.16 input data bus and gram data mapping in 9-bit bus system interface with 18 bit-data.. 36 figure 4.17: example of i80 system 8-bit parallel bus interface type i .................................................... 37 figure 4.18: example of i80 system 8-bit parallel bus interface type ii ................................................... 37 figure 4.19: input data bus and gram data mapping in 8-bit bus system interface with 16-bit-data..... 37 figure 4.20: input data bus and gram data mapping in 8-bit bus system interface with 18-bit-data..... 37 figure 4.21: input data bus and gram data mapping in 8-bit bus system interface with 16 bit-data i nput (tri = 0 and im3, im2, im1, im0=0011) ................................................................. 38 figure 4.22: input data bus and gram data mapping in 8-bit bus system interface with 18 bit-data i nput (tri = 1, dfm = 0 and im3, im2, im1, im0=0011) ............................................... 38 figure 4.23: input data bus and gram data mapping in 8-bit bus system interface with 18 bit-data i nput (tri = 1, dfm = 1 and im3, im2, im1, im0=0011) ............................................... 38 figure 4.24: index register read/write timing in 3-wire serial bus system interface........................... 41 figure 4.25: index register read/write timing in 3-wire serial bus system interface........................... 42 figure 4.26: data write timing in 3-wire serial bus system interface .................................................... 43 figure 4.27: index register write timing in 4-wire serial bus system interface..................................... 43 figure 4.28: data write timing in 4-wire serial bus system interface .................................................... 44 figure 4.29: serial peripheral interface data format .............................................................................. 44 figure 4.30: serial peripheral interface protocol in command write operation ..................................... 45 figure 4.31: serial peripheral interface protocol in gram write operation ........................................... 45 figure 4.32: command read operation in serial peripheral interface ................................................... 46 figure 4.33: write data for rgb 5-6-5-bits (65k colors) input (tri=0)................................................... 47 figure 4.34: write data for rgb 6-6-6-bits(262k colors) (tri=1)........................................................... 47 figure 4.35: vsync interface to mpu..................................................................................................... 48 figure 4.36: vsync interface with internal clock and system interface with internal clock ................. 50 figure 4.37: rgb interface circuit input timing diagram........................................................................ 51 figure 4.38: example of update still and moving picture ........................................................................ 52 figure 4.39: transition between system interface mode and rgb interface mode................................ 53 figure 4.40: ram data write sequence through system interface or rgb interface during rgb ........ 54 figure 4.41: data format for 18-bit interface........................................................................................... 55 figure 4.42: data format for16-bit interface ............................................................................................ 55 figure 4.43: data format for 6-bit interface ............................................................................................. 55 figure 5.1: gram window address mapping example ............................................................................ 59 figure 5.2: te mode 1 output.................................................................................................................. 60 figure 5.3: te delay output..................................................................................................................... 60 figure 5.4: te mode 2 output.................................................................................................................. 61 figure 5.5: te output waveform.............................................................................................................. 61 figure 5.6: waveform of tearing effect signal ........................................................................................ 62 figure 5.7: timing of tearing effect signal .............................................................................................. 62 HX8347-B 240rgb x 320 dot, 262k color, with internal g ram, tft mobile single chip driver list of figures december, 2009 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.6- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. f igure 5.8: timing of mpu write is faster than panel read..................................................................... 63 figure 5.9: display of mpu write is faster than panel read ................................................................... 63 figure 5.10: timing of mpu write is slower than panel read ................................................................. 64 figure 5.11: display of mpu write is slower than panel read ................................................................ 64 figure 5.12: HX8347-B internal clock circuit .......................................................................................... 65 figure 5.13: gate scan mode................................................................................................................... 66 figure 5.14: the block diagram of HX8347-B power circuit .................................................................. 67 figure 5.15: lcd power generation scheme.......................................................................................... 69 figure 5.16: grayscale control ................................................................................................................ 70 figure 5.17: structure of grayscale voltage generator........................................................................... 71 figure 5.18: gamma resister stream and gamma reference voltage.................................................. 73 figure 5.19: relationship between source output and vcom ................................................................. 79 figure 5.20: relationship between gram data and output level (normal white panel rev =1) ...... 79 figure 5.21: display on/off set flow ........................................................................................................ 80 figure 5.22: sleep mode setting flow ...................................................................................................... 81 figure 5.23: standby mode setting flow .................................................................................................. 81 figure 5.24: deep standby mode setting flow......................................................................................... 82 figure 5.25: power supply setting flow .................................................................................................. 83 figure 5.26: example of cabc function................................................................................................... 89 figure 5.27: cabc block diagram............................................................................................................ 89 figure 5.28: cabc_pwm_out output duty ............................................................................................ 91 figure 5.29: dimming function ................................................................................................................. 92 figure 6.1: index register ........................................................................................................................ 98 figure 6.2: driver output control register (r01h)................................................................................... 98 figure 6.3: driving control register (r02h) ........................................................................................... 100 figure 6.4: entry control register (r03h).............................................................................................. 100 figure 6.5: address direction settings................................................................................................... 100 figure 6.6: the setting of dfm and tri (80-system 16-bit interface) ................................................... 101 figure 6.7: the setting of dfm and tri (80-system 8-bit interface) ..................................................... 102 figure 6.8: 16 bits color data mapping register 2 (r05h) ..................................................................... 103 figure 6.9: display control register 1 (r07h) ....................................................................................... 104 figure 6.10: display control register 2 (r08h) ..................................................................................... 105 figure 6.11: display control register 3 (r09h)...................................................................................... 106 figure 6.12: display control register 4 (r0bh) ..................................................................................... 107 figure 6.13: rgb interface control register (r0ch)............................................................................. 108 figure 6.14: te output position (r0dh) ................................................................................................ 109 figure 6.15: rgb interface control register 2 (r0fh) .......................................................................... 109 figure 6.16: power control register 1 (r10h) ........................................................................................110 figure 6.17: power control register 2 (r11h) ........................................................................................112 figure 6.18: power control register 3 (r12h) ........................................................................................113 figure 6.19: power control register 4 (r13h) ........................................................................................114 figure 6.20: ram address register (r20h)............................................................................................114 figure 6.21: ram address register (r21h)............................................................................................114 figure 6.22: read data register (r22h)...................................................................................................115 figure 6.23: output data read from gram through read data register in 18-/16- /9- /8-bit interface116 figure 6.24: power control register 7 (r29h) ........................................................................................117 figure 6.25: frame rate register 7 (r2bh).............................................................................................118 figure 6.26: gamma control register 1~10 (r30h~r3dh)....................................................................118 figure 6.27: get sacn lines register (r45h) ..........................................................................................119 figure 6.28: horizontal ram start address position register (r50h) ....................................................119 figure 6.29: horizontal ram end address position register (r51h) ....................................................119 figure 6.30: vertical ram start address position register (r52h) ........................................................119 figure 6.31: vertical ram end address position register (r53h) ........................................................119 figure 6.32: gate scan position register (r60h).................................................................................. 121 figure 6.33: scn bits and scanning start position for gate driver ...................................................... 122 HX8347-B 240rgb x 320 dot, 262k color, with internal g ram, tft mobile single chip driver list of figures december, 2009 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.7- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. f igure 6.34: base image control register (r61h)...... ........................................................................... 123 figure 6.35: spi read/write control (r66h).......................................................................................... 123 figure 6.36: vertical scroll control (r6ah) ............................................................................................ 124 figure 6.37: partial image 1 display position (r80h) ............................................................................ 124 figure 6.38: partial image 1 area (start line) (r81h)............................................................................ 124 figure 6.39: partial image 1 area (start line) (r81h)............................................................................ 124 figure 6.40: partial image 2 display position (r83h) ............................................................................ 124 figure 6.41: partial image 2 area (start line) (r84h)............................................................................ 125 figure 6.42: partial image 2 area (start line) (r85h)............................................................................ 125 figure 6.43: panel interface control 1 (r90h) ....................................................................................... 127 figure 6.44: panel interface control 2 (r92h) ....................................................................................... 127 figure 6.45: panel interface control 5 (r97h) ....................................................................................... 128 figure 6.46: panel interface control 4 (r98h) ....................................................................................... 128 figure 6.47: otp vcm status and enable (ra2h) ................................................................................ 129 figure 6.48: otp index and mask (ra3h) ............................................................................................. 129 figure 6.49: otp programming id key (ra4h) ..................................................................................... 129 figure 6.50: otp programming id key (ra5h) ..................................................................................... 130 figure 6.51: write display brightness (rb1h)........................................................................................ 130 figure 6.52: read display brightness (rb2h) ....................................................................................... 130 figure 6.53: write ctrl display value (rb3h) ..................................................................................... 130 figure 6.54: read ctrl display value (rb3h) ..................................................................................... 130 figure 6.55: write content adaptive brightness control value (rb5h) ................................................. 130 figure 6.56: read content adaptive brightness control value (rb6h)................................................. 130 figure 6.57: write cabc minimum brightness (rbeh) ......................................................................... 130 figure 6.58: read cabc minimum brightness (rbfh) ......................................................................... 131 figure 6.59: cabc control 1 (rc7h) ..................................................................................................... 132 figure 6.60: cabc control 2 (rbfh) ..................................................................................................... 132 figure 6.61: id1 (rdah)......................................................................................................................... 133 figure 6.62: id2 (rdbh)......................................................................................................................... 133 figure 6.63: id3 (rdch) ........................................................................................................................ 133 figure 6.64: deep stand by control (re6h)............................................................................................ 133 figure 6.65: otp data (rf3h) ............................................................................................................... 133 figure 6.66: otp id cnt (rf4h)........................................................................................................... 133 figure 6.67: otp vcom cnt (rf3h) ................................................................................................... 134 figure 7.1: layout recommendation of HX8347-B................................................................................. 135 figure 8.1: parallel interface characteristics (8080-series mpu) ......................................................... 141 figure 8.2: chip select timing ............................................................................................................... 142 figure 8.3: write to read and read to write timing ............................................................................. 142 figure 8.4: serial interface characteristics ............................................................................................ 143 figure 8.5: reset input timing ............................................................................................................... 146 HX8347-B 240rgb x 320 dot, 262k color, with internal g ram, tft mobile single chip driver list of figures december, 2009 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.8- h imax confidential this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. december, 2009 table 4.1: input bus format selection of system interface circuit.................................................................25 table 4.2: data pin function for i80 series cpu ............................................................................................26 table 4.3: 8-bits parallel interface type i gram write table ..........................................................................29 table 4.4: 16-bits parallel interface type i gram write set table .................................................................29 table 4.5: 9-bits parallel interface type i set gram write table ...................................................................29 table 4.6: 18-bits parallel interface type i gram write set table .................................................................29 table 4.7: 8-bits parallel interface type ii gram write table.........................................................................30 table 4.8: 16-bits parallel interface type ii gram write set table ................................................................30 table 4.9: 9-bits parallel interface type ii set gram write table ..................................................................30 table 4.10: 18-bits parallel interface type ii gram write set table ..............................................................30 table 4.11: 8-bit parallel interface type i gram read table .............................................................................39 table 4.12: 16-bit parallel interface type i gram read table...........................................................................39 table 4.13: 9-bit parallel interface type i gram read table.............................................................................39 table 4.14: 18-bit parallel interface type i gram read table...........................................................................39 table 4.15: 8-bits parallel interface type ii gram read table.......................................................................40 table 4.16: 16-bits parallel interface type ii gram read table.....................................................................40 table 4.17: 9-bits parallel interface type ii gram read table.......................................................................40 table 4.18: 18-bits parallel interface type ii gram read table.....................................................................40 table 4.19: the function of rs and r/w bit bus ...........................................................................................41 table 4.20: dim bit set....................................................................................................................................48 table 5.1: gram address for display panel position ......................................................................................56 table 5.2: gram x address and display panel position.................................................................................57 table 5.3: gram address and display panel position (gs =0).....................................................................58 table 5.4: gram address and display panel position (gs =0).....................................................................58 table 5.5: ac characteristics of tearing effect signal ....................................................................................62 table 5.6: the adoptability of capacitor ..........................................................................................................68 table 5.7: gamma-adjustment registers .......................................................................................................72 table 5.8: offset adjustment 0 ........................................................................................................................74 t able 5.9: offset adjustment 1 ........................................................................................................................74 table 5.10: center adjustment ........................................................................................................................74 table 5.11: output voltage of 8 to 1 selector ..................................................................................................74 table 5.12: voltage calculation formula (positive polarity)............................................................................75 table 5.13: voltage calculation formula of grayscale voltage (positive polarity) .........................................76 table 5.14: voltage calculation formula (negative polarity) ..........................................................................77 table 5.15: voltage calculation formula of grayscale voltage (negative polarity)........................................78 table 5.16: characteristics of output pins ......................................................................................................84 table 5.17: characteristics of input pins .........................................................................................................84 table 6.1: bp/fp bits setting ........................................................................................................................105 table 8.1: absolute maximum ratings ..........................................................................................................138 table 8.2: esd protection level....................................................................................................................138 HX8347-B 240rgb x 320 dot, 262k color, with internal g ram, tft mobile single chip driver list of tables december, 2009 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.9- h imax confidential this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. december, 2009 1. general description this document describes HX8347-B 240rgbx320 dots resolution driving controller. the h x8347-b is designed to provide a single-chip solution that combines a gate driver, a source driver, power supply circuit for 262,144 colors to drive a tft panel with 240rgbx320 dots at m aximum. the HX8347-B can be operated in low-voltage (1.65v) condition for the interface and integrated internal boosters that produce the liquid crystal voltage, breeder resistance and the voltage follower circuit for liquid crystal driver. in addition, the HX8347-B also supports various functions to reduce the power consumption of a lcd system via software control. the HX8347-B is suitable for any small portable battery-driven and long-term driving products, such as small pdas, digital cellular phones and bi-directional pagers. HX8347-B 240rgb x 320 dot, 262k color, with internal g ram, tft mobile single chip driver preliminary version 01 december, 2009 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.10- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 2. features 2.1 display resolution: 240(h) x rgb(h) x 320(v) display color modes normal display mode on 1 . system interface circuit a. full color mode: -262k colours (18bit 6(r):6(g):6(b)) b. reduce color mode: -65k colours (16bit 5(r):6(g):5(b)) 2. rgb interface circuit a. 65,536(r(5),g(6),b(5)) colors b. 262,144(r(6),g(6),b(6)) colors idle mode on - 8 (r(1),g(1),b(1)) colors 2.2 display module frame memory area 240 (h) x 320 (v) x 18 bit on module dc/dc converter ddvdh = 5.0 v for two time pump (power supply for driver circuit range) ddvdh = 6.1 v for three time pump (power supply for driver circuit range) vreg1 = 3.3v to 5.8v (source output voltage range) vgh = +9.0 to +16.5v (positive gate output voltage range) vgl = -6.0 to -13.5v (negative gate output voltage range) on module vcom control (-2.0 to 5.5v common electrode output voltage range) 2.3 display control interface display interface types supported system interface: 1 . 8-/9-/16-/18-bit parallel bus system interface 2. 3-/4-wire serial bus system interface rgb interface: 1 . 6-/16-/18-bit rgb interface color modes 16 bit/pixel: r(5), g(6), b(5) 18 bit/pixel: r(6), g(6), b(6) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.11- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 2.4 input power logic power supply (iovcc): 1.65v ~ 3.3v analog power supply (vci): 2.5v ~ 3.3v outputs source outputs: 720 source lines. selectable gate line control signal for glass 320 gate lines adjusted source voltages (v0p ~v63p, v0n ~v63n) display interface: system interface: a. 8-/9-/16-/18-bit parallel bus system interface b. 3-wire 24bits/3-wire 9bits/4-wire 8bits serial bus system interface c. vsync interface rgb interface: a. 6-/16-/18-bit rgb interface 2 .5 miscellaneous low power consumption, suitable for battery operated systems image sticking eliminated function cmos compatible inputs optimized layout for cog assembly proprietary multi phase driving for lower power consumption support external vddd for lower power consumption (such as 1.8 volts input) support line inversion or frame inversion support area scrolling support partial display mode support deep standby mode support normal black/normal white lcd support wide view angle display audible noise reducing function on-chip otp (one-time-programming) and mtp(8-time-programming for some register) n on-volatile memory support content adaptive brightness control(cabc) function operating temperature range : -40 ~ 85 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.12- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 3. block diagram 3.1 block diagram ncs mpu if s erial if gate dri ver grayscale voltage g enerator vtest gamma adjusting circuit source d river d/a converter ci rcuit data latch c11p/ c11n s1 ~ s720 internal re gister otp gram control gram timing co ntrol step up1 cabc step up2 st ep up3 c 12p / c 12n ddvdh c21p/ c21n c22p/ c22n v gh v gl c31p/ c31n v cl vcom cricuit v c om nrd nw r_scl dnc v0~63 g 1~g320 vgh/vgl im3~im0 nreset de vsync hsync 2 test 2~1 te sto 15 ~3 13 4 vssd v ssa generator timing r c o s c osc power re gulator vddd 18 db 17~0 dotclk 18-bit 1 6-bit 8-bit 9-bit sdi_sda mpu if s erial if rgb if 1 8-bit 16-bit 6-bit ledpwm ledon sd o f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.13- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 3.2 pin description interface logic pin signals i/o pin number connected with description im3, im2,im1,im0 i 4 vssd/ iovcc system interface select. im3 im2 im1 im0 interface 0 0 0 0 8080 mcu 16-bit parallel type i 0 0 0 1 8080 mcu 8-bit parallel type i 0 0 1 0 8080 mcu 16-bits parallel type ii 0 0 1 1 8080 mcu 8-bits parallel type ii 0 1 0 id 3-wire 24-bits serial interface 0 1 1 0 3-wire 9-bits serial interface 0 1 1 1 4-wire 8-bits serial interface 1 0 0 0 8080 mcu 18-bit parallel type i 1 0 0 1 8080 mcu 9-bit parallel type i 1 0 1 0 8080 mcu 18-bits parallel type ii 1 0 1 1 8080 mcu 9-bits parallel type ii if not used, please fix this pin to iovcc or vssd level. ncs i 1 mpu chip select signal. l ow: chip can be accessed; high: chip cannot be accessed. nwr_scl i 1 mpu (nwr) write enable pin i80 parallel bus system interface. (scl) server as serial data clock in serial bus system interface. if not used, connected to iovcc. nrd i 1 mpu (nrd) read enable pin i80 parallel bus system interface. i f not used, connected to iovcc. sdi_sda i 1 mpu serial data input pin in serial bus system interface. the data is inputted on the rising edge of the scl signal. in the 8/9-bit serial peripheral interface, this pin is used as bi-directional data pin. if not used, please connect to vssd or let it open. dnc i 1 mpu (dnc) command / parameter or display data selection pin. i f not used, please connect to vssd or let it open. vsync i 1 mpu vertical synchronizing signal in rgb interface. i f not used, please connect to vssd or let it open. hsync i 1 mpu horizontal synchronizing signal in rgb interface. i f not used, please connect to vssd or let it open. de i 1 mpu a data enable signal in rgb i/f mode. i f not used, please connect to vssd or let it open. dotclk i 1 mpu data enable signal in rgb interface. i f not used, please connect to vssd or let it open. nreset i 1 mpu or reset circuit reset pin. setting either pin low initializes the lsi. must be reset after power is supplied. db17~0 i/o 18 mpu 18-bit bi-directional data bus. the unused pins should be left open or connected to vssd. vgs i 2 vssd or external resistor connect to a variable resistor to adjust the internal gamma reference voltage for matching the characteristic of different panel used. output part signals i/o pin number connected with description s1~s720 o 720 lcd output voltages applied to the liquid crystal. g1~g320 o 320 lcd gate driver output pins. these pins output vgh, vgl.(if not used, s hould be open) vcom o 7 tft common electrode the power supply of common voltage in tft driving. the voltage a mplitude between vcomh and vcoml is output. connect this pin to the common electrode in tft panel. sdo o 1 mpu serial data output pin in serial bus system interface. i f not used, please let it open. te o 1 mpu or open tearing effect output. i f not used, please let it open. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.14- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 ledpwm/testo1 o 1 backlight c ircuit cabc backlight control pwm signal output leden/testo2 o 1 backlight c ircuit this pin is connected to external led driver. its a led driver control pin which is used for turning on/off of led backlight. input/output part signals i/o pin number connected with description c11p,c11n c12p, c12n i/o 5,5 5,5 step-up capacitor connect to the step-up capacitors according to the step-up 1 factor. leave this pin open if the internal step-up circuit is not used. c13p,c13n i/o 4,4 step-up capacitor connect to the step-up capacitors for step up circuit 3 operation . leave this pin open if the internal step-up circuit is not used. c21p,c21n c22p,c22n i/o 7,7 7,7 step-up capacitor connect these pins to the capacitors for the step-up circuit 2. according to the step-up rate. when not using the step-up circuit2, disconnect them. power part signals i/o pin number connected with description iovcc p 6 power supply digital io pad power supply. vci p 21 power supply analog power supply. vssd p 14 ground digital ground. vssa p 8 ground analog ground. vddd o 11 stabilizing capacitor output from internal logic voltage ( 1.6v) . connect to a stabilizing ca pacitor between vssd and vddd vreg1 o 4 open internal generated stable power for source driver unit. leave it open. vcl o 5 stabilizing capacitor an output from the step-up circuit3. a negative voltage for vcoml circuit, vcl= -vci. connect to a stabilizing capacitor between vssa and vcl. ddvdh o 6 stabilizing capacitor an output from the step-up circuit1. c onnect to a stabilizing capacitor between vssa and ddvdh. vgh o 6 stabilizing capacitor a positive power output from the step-up circuit 2 for the gate line d rive circuit. the step-up rate is determined by bt[2:0] bits. connect to a stabilizing capacitor between gnd and vgh. vgl o 10 stabilizing capacitor a negative power output from the step-up circuit 2 for the gate line d rive circuit. the step-up rate is determined by bt[2:0] bits. connect to a stabilizing capacitor between gnd and vgl. test pin and others signals i/o pin number connected with description test2-1 i 2 gnd test pin input (internal pull low). disconnect it. testo15-3 o 13 open a test pin. disconnect it. osc i 1 open or connect to vssd oscillator input for test purpose. i f not used, please let it open or connected to vssd. vtest o 1 open gamma voltage of panel test pin output. must leave it opens. vcomhdum - 6 open dummy pads. leave it open. vcomldum - 7 open dummy pads. leave it open. dummy37-1 - 37 open dummy pads. leave it open. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.15- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 3.3 pin assignment f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.16- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 3.4 pad coordinates no. pad name x y no. pad name x y no. pad name x y no. pad name x y 1 dummy1 -8610 -263 61 dummy7 -4130 -263 121 vcoml 70 -263 181 c11p 4270 -263 2 test1 -8540 -263 62 dummy8 -4060 -263 122 vcoml 140 -263 182 c11p 4340 -263 3 vssd -8470 -263 63 dummy9 -3990 -263 123 vcoml 210 -263 183 c11p 4410 -263 4 ledpwm/testo1 -8400 -263 64 dummy10 -3920 -263 124 vcoml 280 -263 184 c11p 4480 -263 5 ledon/testo2 -8330 -263 65 dummy11 -3850 -263 125 vreg1out 350 -263 185 vgl 4550 -263 6 testo3 -8260 -263 66 osc -3780 -263 126 vreg1out 420 -263 186 vgl 4620 -263 7 im0 -8190 -263 67 iovcc -3710 -263 127 vreg1out 490 -263 187 vgl 4690 -263 8 im1 -8120 -263 68 iovcc -3640 -263 128 vtestout 560 -263 188 vgl 4760 -263 9 im2 -8050 -263 69 iovcc -3570 -263 129 dummy16 630 -263 189 vgl 4830 -263 10 im3 -7980 -263 70 iovcc -3500 -263 130 dummy17 700 -263 190 vgl 4900 -263 11 test2 -7910 -263 71 iovcc -3430 -263 131 vcl 770 -263 191 vgl 4970 -263 12 testo4 -7840 -263 72 iovcc -3360 -263 132 vcl 840 -263 192 vgl 5040 -263 13 testo5 -7770 -263 73 vddd -3290 -263 133 vcl 910 -263 193 vgl 5110 -263 14 testo6 -7700 -263 74 vddd -3220 -263 134 vcl 980 -263 194 vgl 5180 -263 15 testo7 -7630 -263 75 vddd -3150 -263 135 vcl 1050 -263 195 vssd 5250 -263 16 testo8 -7560 -263 76 vddd -3080 -263 136 ddvdh 1120 -263 196 vssd 5320 -263 17 testo9 -7490 -263 77 vddd -3010 -263 137 ddvdh 1190 -263 197 vssd 5390 -263 18 testo10 -7420 -263 78 vddd -2940 -263 138 ddvdh 1260 -263 198 vgh 5460 -263 19 nreset -7350 -263 79 vddd -2870 -263 139 ddvdh 1330 -263 199 vgh 5530 -263 20 nreset -7280 -263 80 vddd -2800 -263 140 ddvdh 1400 -263 200 vgh 5600 -263 21 vsync -7210 -263 81 vddd -2730 -263 141 ddvdh 1470 -263 201 vgh 5670 -263 22 hsync -7140 -263 82 vddd -2660 -263 142 vci 1540 -263 202 vgh 5740 -263 23 dotclk -7070 -263 83 vddd -2590 -263 143 vci 1610 -263 203 vgh 5810 -263 24 de -7000 -263 84 dummy12 -2520 -263 144 vci 1680 -263 204 dummy20 5880 -263 25 db17 -6905 -263 85 vssa -2450 -263 145 vci 1750 -263 205 dummy21 5950 -263 26 db16 -6825 -263 86 vssa -2380 -263 146 vci 1820 -263 206 c13n 6020 -263 27 db15 -6745 -263 87 vssa -2310 -263 147 vci 1890 -263 207 c13n 6090 -263 28 db14 -6665 -263 88 vssa -2240 -263 148 vci 1960 -263 208 c13n 6160 -263 29 db13 -6585 -263 89 vssa -2170 -263 149 vci 2030 -263 209 c13n 6230 -263 30 testo11 -6495 -263 90 vssa -2100 -263 150 vci 2100 -263 210 c13p 6300 -263 31 db12 -6405 -263 91 vssa -2030 -263 151 vci 2170 -263 211 c13p 6370 -263 32 db11 -6325 -263 92 vssa -1960 -263 152 vci 2240 -263 212 c13p 6440 -263 33 db10 -6245 -263 93 vgs -1890 -263 153 vci 2310 -263 213 c13p 6510 -263 34 db9 -6165 -263 94 vgs -1820 -263 154 vci 2380 -263 214 c21n 6580 -263 35 db8 -6085 -263 95 vssd -1750 -263 155 vci 2450 -263 215 c21n 6650 -263 36 dummy2 -5990 -263 96 vssd -1680 -263 156 vci 2520 -263 216 c21n 6720 -263 37 testo12 -5920 -263 97 vssd -1610 -263 157 vci 2590 -263 217 c21n 6790 -263 38 db7 -5825 -263 98 vssd -1540 -263 158 vci 2660 -263 218 c21n 6860 -263 39 db6 -5745 -263 99 vssd -1470 -263 159 vci 2730 -263 219 c21n 6930 -263 40 db5 -5665 -263 100 vssd -1400 -263 160 vci 2800 -263 220 c21n 7000 -263 41 db4 -5585 -263 101 vssd -1330 -263 161 vci 2870 -263 221 c21p 7070 -263 42 db3 -5505 -263 102 vssd -1260 -263 162 vci 2940 -263 222 c21p 7140 -263 43 db2 -5425 -263 103 vssd -1190 -263 163 dummy18 3010 -263 223 c21p 7210 -263 44 db1 -5345 -263 104 vssd -1120 -263 164 dummy19 3080 -263 224 c21p 7280 -263 45 db0 -5265 -263 105 dummy13 -1050 -263 165 c12n 3150 -263 225 c21p 7350 -263 46 testo13 -5180 -263 106 dummy14 -980 -263 166 c12n 3220 -263 226 c21p 7420 -263 47 sdo -5110 -263 107 dummy15 -910 -263 167 c12n 3290 -263 227 c21p 7490 -263 48 sdi_sda -5040 -263 108 vcom -840 -263 168 c12n 3360 -263 228 c22n 7560 -263 49 nrd -4970 -263 109 vcom -770 -263 169 c12n 3430 -263 229 c22n 7630 -263 50 nwr/scl -4900 -263 110 vcom -700 -263 170 c12p 3500 -263 230 c22n 7700 -263 51 dnc -4830 -263 111 vcom -630 -263 171 c12p 3570 -263 231 c22n 7770 -263 52 ncs -4760 -263 112 vcom -560 -263 172 c12p 3640 -263 232 c22n 7840 -263 53 testo14 -4690 -263 113 vcom -490 -263 173 c12p 3710 -263 233 c22n 7910 -263 54 testo15 -4620 -263 114 vcom -420 -263 174 c12p 3780 -263 234 c22n 7980 -263 55 te -4550 -263 115 vcomh -350 -263 175 c11n 3850 -263 235 c22p 8050 -263 56 testo16 -4480 -263 116 vcomh -280 -263 176 c11n 3920 -263 236 c22p 8120 -263 57 dummy3 -4410 -263 117 vcomh -210 -263 177 c11n 3990 -263 237 c22p 8190 -263 58 dummy4 -4340 -263 118 vcomh -140 -263 178 c11n 4060 -263 238 c22p 8260 -263 59 dummy5 -4270 -263 119 vcomh -70 -263 179 c11n 4130 -263 239 c22p 8330 -263 60 dummy6 -4200 -263 120 vcomh 0 -263 180 c11p 4200 -263 240 c22p 8400 -263 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.17- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 no. pad name x y no. pad name x y no. pad name x y no. pad name x y 241 c22p 8470 -263 301 g208 7747 254 361 g88 6787 254 421 s706 5807 137 242 conn 8540 -263 302 g206 7731 137 362 g86 6771 137 422 s705 5791 254 243 conn 8610 -263 303 g204 7715 254 363 g84 6755 254 423 s704 5775 137 244 dummy30 8659 137 304 g202 7699 137 364 g82 6739 137 424 s703 5759 254 245 g320 8643 254 305 g200 7683 254 365 g80 6723 254 425 s702 5743 137 246 g318 8627 137 306 g198 7667 137 366 g78 6707 137 426 s701 5727 254 247 g316 8611 254 307 g196 7651 254 367 g76 6691 254 427 s700 5711 137 248 g314 8595 137 308 g194 7635 137 368 g74 6675 137 428 s699 5695 254 249 g312 8579 254 309 g192 7619 254 369 g72 6659 254 429 s698 5679 137 250 g310 8563 137 310 g190 7603 137 370 g70 6643 137 430 s697 5663 254 251 g308 8547 254 311 g188 7587 254 371 g68 6627 254 431 s696 5647 137 252 g306 8531 137 312 g186 7571 137 372 g66 6611 137 432 s695 5631 254 253 g304 8515 254 313 g184 7555 254 373 g64 6595 254 433 s694 5615 137 254 g302 8499 137 314 g182 7539 137 374 g62 6579 137 434 s693 5599 254 255 g300 8483 254 315 g180 7523 254 375 g60 6563 254 435 s692 5583 137 256 g298 8467 137 316 g178 7507 137 376 g58 6547 137 436 s691 5567 254 257 g296 8451 254 317 g176 7491 254 377 g56 6531 254 437 s690 5551 137 258 g294 8435 137 318 g174 7475 137 378 g54 6515 137 438 s689 5535 254 259 g292 8419 254 319 g172 7459 254 379 g52 6499 254 439 s688 5519 137 260 g290 8403 137 320 g170 7443 137 380 g50 6483 137 440 s687 5503 254 261 g288 8387 254 321 g168 7427 254 381 g48 6467 254 441 s686 5487 137 262 g286 8371 137 322 g166 7411 137 382 g46 6451 137 442 s685 5471 254 263 g284 8355 254 323 g164 7395 254 383 g44 6435 254 443 s684 5455 137 264 g282 8339 137 324 g162 7379 137 384 g42 6419 137 444 s683 5439 254 265 g280 8323 254 325 g160 7363 254 385 g40 6403 254 445 s682 5423 137 266 g278 8307 137 326 g158 7347 137 386 g38 6387 137 446 s681 5407 254 267 g276 8291 254 327 g156 7331 254 387 g36 6371 254 447 s680 5391 137 268 g274 8275 137 328 g154 7315 137 388 g34 6355 137 448 s679 5375 254 269 g272 8259 254 329 g152 7299 254 389 g32 6339 254 449 s678 5359 137 270 g270 8243 137 330 g150 7283 137 390 g30 6323 137 450 s677 5343 254 271 g268 8227 254 331 g148 7267 254 391 g28 6307 254 451 s676 5327 137 272 g266 8211 137 332 g146 7251 137 392 g26 6291 137 452 s675 5311 254 273 g264 8195 254 333 g144 7235 254 393 g24 6275 254 453 s674 5295 137 274 g262 8179 137 334 g142 7219 137 394 g22 6259 137 454 s673 5279 254 275 g260 8163 254 335 g140 7203 254 395 g20 6243 254 455 s672 5263 137 276 g258 8147 137 336 g138 7187 137 396 g18 6227 137 456 s671 5247 254 277 g256 8131 254 337 g136 7171 254 397 g16 6211 254 457 s670 5231 137 278 g254 8115 137 338 g134 7155 137 398 g14 6195 137 458 s669 5215 254 279 g252 8099 254 339 g132 7139 254 399 g12 6179 254 459 s668 5199 137 280 g250 8083 137 340 g130 7123 137 400 g10 6163 137 460 s667 5183 254 281 g248 8067 254 341 g128 7107 254 401 g8 6147 254 461 s666 5167 137 282 g246 8051 137 342 g126 7091 137 402 g6 6131 137 462 s665 5151 254 283 g244 8035 254 343 g124 7075 254 403 g4 6115 254 463 s664 5135 137 284 g242 8019 137 344 g122 7059 137 404 g2 6099 137 464 s663 5119 254 285 g240 8003 254 345 g120 7043 254 405 dummy31 6083 254 465 s662 5103 137 286 g238 7987 137 346 g118 7027 137 406 dummy32 6047 254 466 s661 5087 254 287 g236 7971 254 347 g116 7011 254 407 s720 6031 137 467 s660 5071 137 288 g234 7955 137 348 g114 6995 137 408 s719 6015 254 468 s659 5055 254 289 g232 7939 254 349 g112 6979 254 409 s718 5999 137 469 s658 5039 137 290 g230 7923 137 350 g110 6963 137 410 s717 5983 254 470 s657 5023 254 291 g228 7907 254 351 g108 6947 254 411 s716 5967 137 471 s656 5007 137 292 g226 7891 137 352 g106 6931 137 412 s715 5951 254 472 s655 4991 254 293 g224 7875 254 353 g104 6915 254 413 s714 5935 137 473 s654 4975 137 294 g222 7859 137 354 g102 6899 137 414 s713 5919 254 474 s653 4959 254 295 g220 7843 254 355 g100 6883 254 415 s712 5903 137 475 s652 4943 137 296 g218 7827 137 356 g98 6867 137 416 s711 5887 254 476 s651 4927 254 297 g216 7811 254 357 g96 6851 254 417 s710 5871 137 477 s650 4911 137 298 g214 7795 137 358 g94 6835 137 418 s709 5855 254 478 s649 4895 254 299 g212 7779 254 359 g92 6819 254 419 s708 5839 137 479 s648 4879 137 300 g210 7763 137 360 g90 6803 137 420 s707 5823 254 480 s647 4863 254 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.18- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 no. pad name x y no. pad name x y no. pad name x y no. pad name x y 481 s646 4847 137 541 s586 3887 137 601 s526 2927 137 661 s466 1967 137 482 s645 4831 254 542 s585 3871 254 602 s525 2911 254 662 s465 1951 254 483 s644 4815 137 543 s584 3855 137 603 s524 2895 137 663 s464 1935 137 484 s643 4799 254 544 s583 3839 254 604 s523 2879 254 664 s463 1919 254 485 s642 4783 137 545 s582 3823 137 605 s522 2863 137 665 s462 1903 137 486 s641 4767 254 546 s581 3807 254 606 s521 2847 254 666 s461 1887 254 487 s640 4751 137 547 s580 3791 137 607 s520 2831 137 667 s460 1871 137 488 s639 4735 254 548 s579 3775 254 608 s519 2815 254 668 s459 1855 254 489 s638 4719 137 549 s578 3759 137 609 s518 2799 137 669 s458 1839 137 490 s637 4703 254 550 s577 3743 254 610 s517 2783 254 670 s457 1823 254 491 s636 4687 137 551 s576 3727 137 611 s516 2767 137 671 s456 1807 137 492 s635 4671 254 552 s575 3711 254 612 s515 2751 254 672 s455 1791 254 493 s634 4655 137 553 s574 3695 137 613 s514 2735 137 673 s454 1775 137 494 s633 4639 254 554 s573 3679 254 614 s513 2719 254 674 s453 1759 254 495 s632 4623 137 555 s572 3663 137 615 s512 2703 137 675 s452 1743 137 496 s631 4607 254 556 s571 3647 254 616 s511 2687 254 676 s451 1727 254 497 s630 4591 137 557 s570 3631 137 617 s510 2671 137 677 s450 1711 137 498 s629 4575 254 558 s569 3615 254 618 s509 2545 254 678 s449 1695 254 499 s628 4559 137 559 s568 3599 137 619 s508 2639 137 679 s448 1679 137 500 s627 4543 254 560 s567 3583 254 620 s507 2623 254 680 s447 1663 254 501 s626 4527 137 561 s566 3567 137 621 s506 2607 137 681 s446 1647 137 502 s625 4511 254 562 s565 3551 254 622 s505 2591 254 682 s445 1631 254 503 s624 4495 137 563 s564 3535 137 623 s504 2575 137 683 s444 1615 137 504 s623 4479 254 564 s563 3519 254 624 s503 2559 254 684 s443 1599 254 505 s622 4463 137 565 s562 3503 137 625 s502 2543 137 685 s442 1583 137 506 s621 4447 254 566 s561 3487 254 626 s501 2527 254 686 s441 1567 254 507 s620 4431 137 567 s560 3471 137 627 s500 2511 137 687 s440 1551 137 508 s619 4415 254 568 s559 3455 254 628 s499 2495 254 688 s439 1535 254 509 s618 4399 137 569 s558 3439 137 629 s498 2479 137 689 s438 1519 137 510 s617 4383 254 570 s557 3423 254 630 s497 2463 254 690 s437 1503 254 511 s616 4367 137 571 s556 3407 137 631 s496 2447 137 691 s436 1377 137 512 s615 4351 254 572 s555 3391 254 632 s495 2431 254 692 s435 1471 254 513 s614 4335 137 573 s554 3375 137 633 s494 2415 137 693 s434 1455 137 514 s613 4319 254 574 s553 3359 254 634 s493 2399 254 694 s433 1439 254 515 s612 4303 137 575 s552 3343 137 635 s492 2383 137 695 s432 1423 137 516 s611 4287 254 576 s551 3327 254 636 s491 2367 254 696 s431 1407 254 517 s610 4271 137 577 s550 3311 137 637 s490 2351 137 697 s430 1391 137 518 s609 4255 254 578 s549 3295 254 638 s489 2335 254 698 s429 1375 254 519 s608 4239 137 579 s548 3279 137 639 s488 2319 137 699 s428 1359 137 520 s607 4223 254 580 s547 3263 254 640 s487 2303 254 700 s427 1343 254 521 s606 4207 137 581 s546 3247 137 641 s486 2287 137 701 s426 1327 137 522 s605 4191 254 582 s545 3231 254 642 s485 2271 254 702 s425 1311 254 523 s604 4175 137 583 s544 3215 137 643 s484 2255 137 703 s424 1295 137 524 s603 4159 254 584 s543 3199 254 644 s483 2239 254 704 s423 1279 254 525 s602 4143 137 585 s542 3183 137 645 s482 2223 137 705 s422 1263 137 526 s601 4127 254 586 s541 3167 254 646 s481 2207 254 706 s421 1247 254 527 s600 4111 137 587 s540 3151 137 647 s480 2191 137 707 s420 1231 137 528 s599 4095 254 588 s539 3135 254 648 s479 2175 254 708 s419 1215 254 529 s598 4079 137 589 s538 3119 137 649 s478 2159 137 709 s418 1199 137 530 s597 4063 254 590 s537 3103 254 650 s477 2143 254 710 s417 1183 254 531 s596 4047 137 591 s536 3087 137 651 s476 2127 137 711 s416 1167 137 532 s595 4031 254 592 s535 3071 254 652 s475 2111 254 712 s415 1151 254 533 s594 4015 137 593 s534 3055 137 653 s474 2095 137 713 s414 1135 137 534 s593 3999 254 594 s533 3039 254 654 s473 2079 254 714 s413 1119 254 535 s592 3983 137 595 s532 3023 137 655 s472 2063 137 715 s412 1103 137 536 s591 3967 254 596 s531 3007 254 656 s471 2047 254 716 s411 1087 254 537 s590 3951 137 597 s530 2991 137 657 s470 2031 137 717 s410 1071 137 538 s589 3935 254 598 s529 2975 254 658 s469 2015 254 718 s409 1055 254 539 s588 3919 137 599 s528 2959 137 659 s468 1999 137 719 s408 1039 137 540 s587 3903 254 600 s527 2943 254 660 s467 1983 254 720 s407 1023 254 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.19- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 no. pad name x y no. pad name x y no. pad name x y no. pad name x y 721 s406 1007 137 781 s348 -479 254 841 s288 -1439 254 901 s228 -2399 254 722 s405 991 254 782 s347 -495 137 842 s287 -1455 137 902 s227 -2415 137 723 s404 975 137 783 s346 -511 254 843 s286 -1471 254 903 s226 -2431 254 724 s403 959 254 784 s345 -527 137 844 s285 -1487 137 904 s225 -2447 137 725 s402 943 137 785 s344 -543 254 845 s284 -1503 254 905 s224 -2463 254 726 s401 927 254 786 s343 -559 137 846 s283 -1519 137 906 s223 -2479 137 727 s400 911 137 787 s342 -575 254 847 s282 -1535 254 907 s222 -2495 254 728 s399 895 254 788 s341 -591 137 848 s281 -1551 137 908 s221 -2511 137 729 s398 879 137 789 s340 -607 254 849 s280 -1567 254 909 s220 -2527 254 730 s397 863 254 790 s339 -623 137 850 s279 -1583 137 910 s219 -2543 137 731 s396 847 137 791 s338 -639 254 851 s278 -1599 254 911 s218 -2559 254 732 s395 831 254 792 s337 -655 137 852 s277 -1615 137 912 s217 -2575 137 733 s394 815 137 793 s336 -671 254 853 s276 -1631 254 913 s216 -2591 254 734 s393 799 254 794 s335 -687 137 854 s275 -1647 137 914 s215 -2607 137 735 s392 783 137 795 s334 -703 254 855 s274 -1663 254 915 s214 -2623 254 736 s391 767 254 796 s333 -719 137 856 s273 -1679 137 916 s213 -2639 137 737 s390 751 137 797 s332 -735 254 857 s272 -1695 254 917 s212 -2655 254 738 s389 735 254 798 s331 -751 137 858 s271 -1711 137 918 s211 -2671 137 739 s388 719 137 799 s330 -767 254 859 s270 -1727 254 919 s210 -2687 254 740 s387 703 254 800 s329 -783 137 860 s269 -1743 137 920 s209 -2703 137 741 s386 687 137 801 s328 -799 254 861 s268 -1759 254 921 s208 -2719 254 742 s385 671 254 802 s327 -815 137 862 s267 -1775 137 922 s207 -2735 137 743 s384 655 137 803 s326 -831 254 863 s266 -1791 254 923 s206 -2751 254 744 s383 639 254 804 s325 -847 137 864 s265 -1807 137 924 s205 -2767 137 745 s382 623 137 805 s324 -863 254 865 s264 -1823 254 925 s204 -2783 254 746 s381 607 254 806 s323 -879 137 866 s263 -1839 137 926 s203 -2799 137 747 s380 591 137 807 s322 -895 254 867 s262 -1855 254 927 s202 -2815 254 748 s379 575 254 808 s321 -911 137 868 s261 -1871 137 928 s201 -2831 137 749 s378 559 137 809 s320 -927 254 869 s260 -1887 254 929 s200 -2847 254 750 s377 543 254 810 s319 -943 137 870 s259 -1903 137 930 s199 -2863 137 751 s376 527 137 811 s318 -959 254 871 s258 -1919 254 931 s198 -2879 254 752 s375 511 254 812 s317 -975 137 872 s257 -1935 137 932 s197 -2895 137 753 s374 495 137 813 s316 -991 254 873 s256 -1951 254 933 s196 -2911 254 754 s373 479 254 814 s315 -1007 137 874 s255 -1967 137 934 s195 -2927 137 755 s372 463 137 815 s314 -1023 254 875 s254 -1983 254 935 s194 -2943 254 756 s371 447 254 816 s313 -1039 137 876 s253 -1999 137 936 s193 -2959 137 757 s370 431 137 817 s312 -1055 254 877 s252 -2015 254 937 s192 -2975 254 758 s369 415 254 818 s311 -1071 137 878 s251 -2031 137 938 s191 -2991 137 759 s368 399 137 819 s310 -1087 254 879 s250 -2047 254 939 s190 -3007 254 760 s367 383 254 820 s309 -1103 137 880 s249 -2063 137 940 s189 -3023 137 761 s366 367 137 821 s308 -1119 254 881 s248 -2079 254 941 s188 -3039 254 762 s365 351 254 822 s307 -1135 137 882 s247 -2095 137 942 s187 -3055 137 763 s364 335 137 823 s306 -1151 254 883 s246 -2111 254 943 s186 -3071 254 764 s363 319 254 824 s305 -1167 137 884 s245 -2127 137 944 s185 -3087 137 765 s362 303 137 825 s304 -1183 254 885 s244 -2143 254 945 s184 -3103 254 766 s361 287 254 826 s303 -1199 137 886 s243 -2159 137 946 s183 -3119 137 767 dummy33 271 137 827 s302 -1215 254 887 s242 -2175 254 947 s182 -3135 254 768 dummy34 -271 137 828 s301 -1231 137 888 s241 -2191 137 948 s181 -3151 137 769 s360 -287 254 829 s300 -1247 254 889 s240 -2207 254 949 s180 -3167 254 770 s359 -303 137 830 s299 -1263 137 890 s239 -2223 137 950 s179 -3183 137 771 s358 -319 254 831 s298 -1279 254 891 s238 -2239 254 951 s178 -3199 254 772 s357 -335 137 832 s297 -1295 137 892 s237 -2255 137 952 s177 -3215 137 773 s356 -351 254 833 s296 -1311 254 893 s236 -2271 254 953 s176 -3231 254 774 s355 -367 137 834 s295 -1327 137 894 s235 -2287 137 954 s175 -3247 137 775 s354 -383 254 835 s294 -1343 254 895 s234 -2303 254 955 s174 -3263 254 776 s353 -399 137 836 s293 -1359 137 896 s233 -2319 137 956 s173 -3279 137 777 s352 -415 254 837 s292 -1375 254 897 s232 -2335 254 957 s172 -3295 254 778 s351 -431 137 838 s291 -1391 137 898 s231 -2351 137 958 s171 -3311 137 779 s350 -447 254 839 s290 -1407 254 899 s230 -2367 254 959 s170 -3327 254 780 s349 -463 137 840 s289 -1423 137 900 s229 -2383 137 960 s169 -3343 137 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.20- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 no. pad name x y no. pad name x y no. pad name x y no. pad name x y 961 s168 -3359 254 1021 s108 -4319 254 1081 s48 -5279 254 1141 g21 -6259 137 962 s167 -3375 137 1022 s107 -4335 137 1082 s47 -5295 137 1142 g23 -6275 254 963 s166 -3391 254 1023 s106 -4351 254 1083 s46 -5311 254 1143 g25 -6291 137 964 s165 -3407 137 1024 s105 -4367 137 1084 s45 -5327 137 1144 g27 -6307 254 965 s164 -3423 254 1025 s104 -4383 254 1085 s44 -5343 254 1145 g29 -6323 137 966 s163 -3439 137 1026 s103 -4399 137 1086 s43 -5359 137 1146 g31 -6339 254 967 s162 -3455 254 1027 s102 -4415 254 1087 s42 -5375 254 1147 g33 -6355 137 968 s161 -3471 137 1028 s101 -4431 137 1088 s41 -5391 137 1148 g35 -6371 254 969 s160 -3487 254 1029 s100 -4447 254 1089 s40 -5407 254 1149 g37 -6387 137 970 s159 -3503 137 1030 s99 -4463 137 1090 s39 -5423 137 1150 g39 -6403 254 971 s158 -3519 254 1031 s98 -4479 254 1091 s38 -5439 254 1151 g41 -6419 137 972 s157 -3535 137 1032 s97 -4495 137 1092 s37 -5455 137 1152 g43 -6435 254 973 s156 -3551 254 1033 s96 -4511 254 1093 s36 -5471 254 1153 g45 -6451 137 974 s155 -3567 137 1034 s95 -4527 137 1094 s35 -5487 137 1154 g47 -6467 254 975 s154 -3583 254 1035 s94 -4543 254 1095 s34 -5503 254 1155 g49 -6483 137 976 s153 -3599 137 1036 s93 -4559 137 1096 s33 -5519 137 1156 g51 -6499 254 977 s152 -3615 254 1037 s92 -4575 254 1097 s32 -5535 254 1157 g53 -6515 137 978 s151 -3631 137 1038 s91 -4591 137 1098 s31 -5551 137 1158 g55 -6531 254 979 s150 -3647 254 1039 s90 -4607 254 1099 s30 -5567 254 1159 g57 -6547 137 980 s149 -3663 137 1040 s89 -4623 137 1100 s29 -5583 137 1160 g59 -6563 254 981 s148 -3679 254 1041 s88 -4639 254 1101 s28 -5599 254 1161 g61 -6579 137 982 s147 -3695 137 1042 s87 -4655 137 1102 s27 -5615 137 1162 g63 -6595 254 983 s146 -3711 254 1043 s86 -4671 254 1103 s26 -5631 254 1163 g65 -6611 137 984 s145 -3727 137 1044 s85 -4687 137 1104 s25 -5647 137 1164 g67 -6627 254 985 s144 -3743 254 1045 s84 -4703 254 1105 s24 -5663 254 1165 g69 -6643 137 986 s143 -3759 137 1046 s83 -4719 137 1106 s23 -5679 137 1166 g71 -6659 254 987 s142 -3775 254 1047 s82 -4735 254 1107 s22 -5695 254 1167 g73 -6675 137 988 s141 -3791 137 1048 s81 -4751 137 1108 s21 -5711 137 1168 g75 -6691 254 989 s140 -3807 254 1049 s80 -4767 254 1109 s20 -5727 254 1169 g77 -6707 137 990 s139 -3823 137 1050 s79 -4783 137 1110 s19 -5743 137 1170 g79 -6723 254 991 s138 -3839 254 1051 s78 -4799 254 1111 s18 -5759 254 1171 g81 -6739 137 992 s137 -3855 137 1052 s77 -4815 137 1112 s17 -5775 137 1172 g83 -6755 254 993 s136 -3871 254 1053 s76 -4831 254 1113 s16 -5791 254 1173 g85 -6771 137 994 s135 -3887 137 1054 s75 -4847 137 1114 s15 -5807 137 1174 g87 -6787 254 995 s134 -3903 254 1055 s74 -4863 254 1115 s14 -5823 254 1175 g89 -6803 137 996 s133 -3919 137 1056 s73 -4879 137 1116 s13 -5839 137 1176 g91 -6819 254 997 s132 -3935 254 1057 s72 -4895 254 1117 s12 -5855 254 1177 g93 -6835 137 998 s131 -3951 137 1058 s71 -4911 137 1118 s11 -5871 137 1178 g95 -6851 254 999 s130 -3967 254 1059 s70 -4927 254 1119 s10 -5887 254 1179 g97 -6867 137 1000 s129 -3983 137 1060 s69 -4943 137 1120 s9 -5903 137 1180 g99 -6883 254 1001 s128 -3999 254 1061 s68 -4959 254 1121 s8 -5919 254 1181 g101 -6899 137 1002 s127 -4015 137 1062 s67 -4975 137 1122 s7 -5935 137 1182 g103 -6915 254 1003 s126 -4031 254 1063 s66 -4991 254 1123 s6 -5951 254 1183 g105 -6931 137 1004 s125 -4047 137 1064 s65 -5007 137 1124 s5 -5967 137 1184 g107 -6947 254 1005 s124 -4063 254 1065 s64 -5023 254 1125 s4 -5983 254 1185 g109 -6963 137 1006 s123 -4079 137 1066 s63 -5039 137 1126 s3 -5999 137 1186 g111 -6979 254 1007 s122 -4095 254 1067 s62 -5055 254 1127 s2 -6015 254 1187 g113 -6995 137 1008 s121 -4111 137 1068 s61 -5071 137 1128 s1 -6031 137 1188 g115 -7011 254 1009 s120 -4127 254 1069 s60 -5087 254 1129 dummy35 -6047 254 1189 g117 -7027 137 1010 s119 -4143 137 1070 s59 -5103 137 1130 dummy36 -6083 254 1190 g119 -7043 254 1011 s118 -4159 254 1071 s58 -5119 254 1131 g1 -6099 137 1191 g121 -7059 137 1012 s117 -4175 137 1072 s57 -5135 137 1132 g3 -6115 254 1192 g123 -7075 254 1013 s116 -4191 254 1073 s56 -5151 254 1133 g5 -6131 137 1193 g125 -7091 137 1014 s115 -4207 137 1074 s55 -5167 137 1134 g7 -6147 254 1194 g127 -7107 254 1015 s114 -4223 254 1075 s54 -5183 254 1135 g9 -6163 137 1195 g129 -7123 137 1016 s113 -4239 137 1076 s53 -5199 137 1136 g11 -6179 254 1196 g131 -7139 254 1017 s112 -4255 254 1077 s52 -5215 254 1137 g13 -6195 137 1197 g133 -7155 137 1018 s111 -4271 137 1078 s51 -5231 137 1138 g15 -6211 254 1198 g135 -7171 254 1019 s110 -4287 254 1079 s50 -5247 254 1139 g17 -6227 137 1199 g137 -7187 137 1020 s109 -4303 137 1080 s49 -5263 137 1140 g19 -6243 254 1200 g139 -7203 254 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.21- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 no. pad name x y no. pad name x y 1201 g141 -7219 137 1261 g261 -8179 137 1202 g143 -7235 254 1262 g263 -8195 254 1203 g145 -7251 137 1263 g265 -8211 137 1204 g147 -7267 254 1264 g267 -8227 254 1205 g149 -7283 137 1265 g269 -8243 137 1206 g151 -7299 254 1266 g271 -8259 254 1207 g153 -7315 137 1267 g273 -8275 137 1208 g155 -7331 254 1268 g275 -8291 254 1209 g157 -7347 137 1269 g277 -8307 137 1210 g159 -7363 254 1270 g279 -8323 254 1211 g161 -7379 137 1271 g281 -8339 137 1212 g163 -7395 254 1272 g283 -8355 254 1213 g165 -7411 137 1273 g285 -8371 137 1214 g167 -7427 254 1274 g287 -8387 254 1215 g169 -7443 137 1275 g289 -8403 137 1216 g171 -7459 254 1276 g291 -8419 254 1217 g173 -7475 137 1277 g293 -8435 137 1218 g175 -7491 254 1278 g295 -8451 254 1219 g177 -7507 137 1279 g297 -8467 137 1220 g179 -7523 254 1280 g299 -8483 254 1221 g181 -7539 137 1281 g301 -8499 137 1222 g183 -7555 254 1282 g303 -8515 254 1223 g185 -7571 137 1283 g305 -8531 137 1224 g187 -7587 254 1284 g307 -8547 254 1225 g189 -7603 137 1285 g309 -8563 137 1226 g191 -7619 254 1286 g311 -8579 254 1227 1228 g193 -7635 137 1287 g313 -8595 137 1228 g195 -7651 254 1288 g315 -8611 254 1229 g197 -7667 137 1289 g317 -8627 137 1230 g199 -7683 254 1290 g319 -8643 254 1231 g201 -7699 137 1291 dummy37 -8659 137 1232 g203 -7715 254 1233 g205 -7731 137 alignment mark x y 1234 g207 -7747 254 a1 -8751 214.5 1235 g209 -7763 137 a2 8751 214.5 1236 g211 -7779 254 1237 g213 -7795 137 1238 g215 -7811 254 1239 g217 -7827 137 1240 g219 -7843 254 1241 g221 -7859 137 1242 g223 -7875 254 1243 g225 -7891 137 1244 g227 -7907 254 1245 g229 -7923 137 1246 g231 -7939 254 1247 g233 -7955 137 1248 g235 -7971 254 1249 g237 -7987 137 1250 g239 -8003 254 1251 g241 -8019 137 1252 g243 -8035 254 1253 g245 -8051 137 1254 g247 -8067 254 1255 g249 -8083 137 1256 g251 -8099 254 1257 g253 -8115 137 1258 g255 -8131 254 1259 g257 -8147 137 1260 g259 -8163 254 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.22- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 3.5 bump size i nput pad output pad f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.23- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 3.6 alignment mark 30um 3 0um 15um 20um 15um 10um 10um 30um 1 5um 20um 15um 30um a_mark (a1) 30um 3 0um 15um 20um 15um 10um 10um 30um 1 5um 20um 15um 30um a_mark (a2) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.24- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 4. interface the HX8347-B has a system interface circuit for register command/gram data transferring, a nd a rgb interface circuit for display data transferring during animated display. the system interface circuit uses data bus pins (db17-0). since the data bus pins (db17-0) can be used as input in rgb interface circuit, the HX8347-B shows animated display with less wiring. s ystem interface can be used to access internal command and internal 18-bit/pixel gram. the rgb interface, the display data is written into the gram through the control signals of de, vsync, hsync, dotclk and data bus db[17:0]. the HX8347-B also has vsync interface. in vsync interface mode, the internal display t iming is synchronized with the frame synchronization sign (vsync). the vsync interface mode enables to display the moving picture display through the system interface. in this case, there are some constraints of speed and method to write data to the internal ram. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.25- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 4.1 system interface circuit the system interface circuit in HX8347-B supports 18-/16-/9-/8-bit bus width parallel bus sy stem interface for i80 series cpu, and serial bus system interface for serial data input. when ncs = l, the parallel and serial bus system interface of the HX8347-B become active and data transfer through the interface circuit is available. the dnc_scl pin specifies whether the system interface circuit access is to the register command or to the display data ram. the input bus format of system interface circuit is selected by external pins setting. for selecting the input bus format, please refer to table 4.1. data bus use im3 im2 im1 im0 interface register/content gram 0 0 0 0 8080 mcu 16-bit parallel type i d7-d0 d15-d0: 16-bit data 0 0 0 1 8080 mcu 8-bit parallel type i d7-d0 d7-d0: 8-bit data 0 0 1 0 8080 mcu 16-bits parallel d8-d1 d17-10, d8-d1: 16-bit data 0 0 1 1 8080 mcu 8-bits parallel d17-d10 d17-d10: 8-bits data 0 1 0 id 3-wire 24-bits serial interface sdi, sdo 0 1 1 0 3-wire 9-bits serial interface sdi 0 1 1 1 4-wire serial interface sdi 1 0 0 0 8080 mcu 18-bit parallel type i d7-d0 d17-d0: 18-bit data 1 0 0 1 8080 mcu 9-bit parallel type i d7-d0 d8-d0: 9-bit data 1 0 1 0 8080 mcu 18-bits parallel d8-d1 d17-d0: 18-bits data 1 0 1 1 8080 mcu 9-bits parallel d17-d10 d17-d9: 9-bits data other setting setting invalid table 4.1: input bus format selection of system interface circuit it has an index register (ir) in HX8347-B to store index data of internal control register and g ram. therefore, the ir can be written with the index pointer of the control register through data bus by setting dnc_scl=0. then the command or gram data can be written to register at which that index pointer pointed by setting dnc_scl=1. furthermore, there are two 18-bit bus control registers used to temporarily store the data w ritten to or read from the gram. when the data is written into the gram from the mpu, it is first written into the write-data latch and then automatically written into the gram by internal operation. data is read through the read-data latch when reading from the gram. therefore, the first read data operation is invalid and the following read data operations are valid. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.26- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 4.1.1 parallel bus system interface the input / output data from data pins (db17-0) and signal operation of the i80 series parallel b us interface are listed in table 4.2. operations nwr_scl nrd dnc writes indexes into ir 0 1 0 reads internal status 1 0 0 writes command into register or data into gram 0 1 1 reads command from register or data from gram 1 0 1 table 4.2: data pin function for i80 series cpu f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.27- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 figure 4.1: register read/write timing in parallel bus system interface (for i80 series mpu) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.28- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 dnc ncs "22 " h 1st write data 3 rd write data 4th write data 2nd write data nrd n wr_scl dnc ncs dummy read data "22" h 1st read data 2nd read read 3rd read data nrd n wr_scl db[b:0] db[b:0] 5th write data dnc ncs 22h 1st write data 3 rd write data 4th write data 2nd write data nrd n wr_scl dnc ncs dummy read data 1st read data 2nd read read 3rd read data nrd n wr_scl db[b:0] db[b:0] 5th write data 00h 22h 00h nth pixel (n+1)th pixel nth pixel 4th read data (n +1)th pixel figure 4.2: gram read/write timing in parallel bus sy stem interface (for i80 series mpu) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.29- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 4.1.2 mcu data color coding mcu data color coding for ram data w rite - parallel 8-bits bus interface type i (im3,im2,im1,im0=0001) register db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 command tri dfm x x x x x x x x x x 0 0 1 0 0 0 1 0 22h x x x x x x x x x x r4 r3 r2 r1 r0 g5 g4 g3 0 x x x x x x x x x x x g2 g1 g0 b4 b3 b2 b1 b0 65k-color (1-pixel/ 2-bytes) x x x x x x x x x x r5 r4 r3 r2 r1 r0 x x x x x x x x x x x x g5 g4 g3 g2 g1 g0 x x 1 x x x x x x x x x x x b5 b4 b3 b2 b1 b0 x x 262k-color (1-pixel/ 3bytes) table 4.3: 8-bits parallel interface type i gram write table - parallel 16-bits bus interface type i (im3,im2,im1,im0=0000) register db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 command tri dfm x x x x x x x x x x 0 0 1 0 0 0 1 0 22h 0 x x x r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 65k-color x x r5 r4 r3 r2 r1 r0 x x g5 g4 g3 g2 g1 g0 x x x x b5 b4 b3 b2 b1 b0 x x r5 r4 r3 r2 r1 r0 x x 1 0 x x g5 g4 g3 g2 g1 g0 x x b5 b4 b3 b2 b1 b0 x x 262k-color (2-pixels/ 3bytes) x x r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 1 1 x x x x x x x x x x x x x x x x b1 b0 262k-color (16+2) table 4.4: 16-bits parallel interface type i gram write set table - parallel 9-bits bus interface type i (im3,im2,im1,im0=1001) register d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register tri dfm x x x x x x x x x x 0 0 1 0 0 0 1 0 22h x x x x x x x x x r5 r4 r3 r2 r1 r0 g5 g4 g3 x x x x x x x x x x x g2 g1 g0 b5 b4 b3 b2 b1 b0 262k-color (1-pixels/ 2bytes) table 4.5: 9-bits parallel interface type i set gram write table - parallel 18-bits bus interface type i (im3,im2,im1,im0=1000) register db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 register tri dfm x x x x x x x x x x 0 0 1 0 0 0 1 0 22h x x r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 262k-color table 4.6: 18-bits parallel interface type i gram write set table f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.30- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 - parallel 8-bits bus interface typeii (im3,im2,im1,im0=0011) register db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 command tri dfm 0 0 1 0 0 0 1 0 x x x x x x x x x x 22h r4 r3 r2 r1 r0 g5 g4 g3 x x x x x x x x x x 0 x g2 g1 g0 b4 b3 b2 b1 b0 x x x x x x x x x x 65k-color (1-pixels/ 2-bytes) x x x x x x r5 r4 x x x x x x x x x x r3 r2 r1 r0 g5 g4 g3 g2 x x x x x x x x x x 1 0 g1 g0 b5 b4 b3 b2 b1 b0 x x x x x x x x x x 262k-color (2+8+8) r5 r4 r3 r2 r1 r0 x x x x x x x x x x x x g5 g4 g3 g2 g1 g0 x x x x x x x x x x x x 1 1 b5 b4 b3 b2 b1 b0 x x x x x x x x x x x x 262k-color (6+6+6) table 4.7: 8-bits parallel interface type ii gram write table - parallel 16-bits bus interface typeii (im3,im2,im1,im0=0010) register db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 command tri dfm x 0 0 1 0 0 0 1 0 x 22h 0 x r4 r3 r2 r1 r0 g5 g4 g3 x g2 g1 g0 b4 b3 b2 b1 b0 x 65k-color r5 r4 r3 r2 r1 r0 g5 g4 x g3 g2 g1 g0 b5 b4 b3 b2 x 1 0 b1 b0 x x x x x x x x x x x x x x x x 262k-color (16+2) x x x x x x x x x x x x x x x r5 r4 x 1 1 r3 r2 r1 r0 g5 g4 g3 g2 x g1 g0 b5 b4 b3 b2 b1 b0 x 262k-color (2+16) table 4.8: 16-bits parallel interface type ii gram write set table - parallel 9-bits bus interface typeii (im3,im2,im1,im0=1011) register d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register tri dfm 0 0 1 0 0 0 1 0 x x x x x x x x x x 22h r5 r4 r3 r2 r1 r0 g5 g4 g3 x x x x x x x x x x x g2 g1 g0 b5 b4 b3 b2 b1 b0 x x x x x x x x x 262k-color (1-pixels/ 2bytes) table 4.9: 9-bits parallel interface type ii set gram write table - parallel 18-bits bus interface typeii (im3,im2,im1,im0=1010) register db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 register tri dfm x x x x x x x x x 0 0 1 0 0 0 1 0 x 22h x x r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 262k-color table 4.10: 18-bits parallel interface type ii gram write set table f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.31- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 18-bit parallel bus system interface t he i80-system 18-bit parallel bus interface type i in command-parameter interface mode can be used by setting external pins im3, im2, im1, im0 pins to 1000. and the i80-system 18-bit parallel bus interface type ii in command-parameter interface mode can be used by setting im3, im2, im1, and im0pins to1010. figure 4.3 is the example of interface with i80 microcomputer system interface. / HX8347-B 18 mpu nwr_scl nrd ncs db17-0 dnc figure 4.3: example of i80- system 18-bit parallel bus interface figure 4.4: input data bus and gram data mapping in 18-bit bus system interface with 18 bit-data input (im3, im2, im1, im=1010 or 1000) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.32- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 16-bit parallel bus system interface the i80-system 16-bit parallel bus interface t ype i in command-parameter interface mode can be used by setting external pins im3, im2, im1, im0 pins to 0000. and i80-system 16-bit parallel bus interface type ii in command-parameter interface mode can be used by setting im3, im2, im1, and im0pins to0010. figure 4.5 is the example of type i interface with i80 microcomputer system interface. and figure 4.6 is the example of type ii interface with i80 microcomputer system interface. figure 4.5: example of i80 system 16-bit parallel bus interface type i figure 4.6: example of i80 system 16-bit parallel bus interface type ii figure 4.7: input data bus and gram data mapping in 16-bit bus system interface with 16-bit-data input (tri = 0 and im3, im2, im1, im0=0000) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.33- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 gram data input data bus transfer order 16-bit data 1 b5 b4 b3 b2 b1 b0 2 62, 144 colors are available db 15 db 14 db 13 db 12 db 11 db 10 db 7 db 6 db 5 db 4 db 3 db 2 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 16-bit data 2 db 1 5 db 14 db 13 db 12 db 11 db 10 db 7 db 6 db 5 db 4 db 3 db 2 r5 r4 r3 r2 r1 r0 1st pixel figure 4.8: input data bus and gram data mapping in 16-bit bus system interface with 18 bit-data input (tri = 1, dfm = 0 and im3, im2, im1, im0=0000) figure 4.9: input data bus and gram data mapping in 16-bit bus system interface with 18(16+2) bit-data input (tri = 1, dfm = 1 and im3, im2, im1, im0=0000) figure 4.10: input data bus and gram data mapping in 16-bit bus system interface with 16 bit-data input (tri = 0 and im3, im2, im1, im0=0010) figure 4.11: input data bus and gram data mapping in 16-bit bus system interface with 18(16+2) bit-data input (tri = 1, dfm = 0 and im3, im2, im1, im0=0010) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.34- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 figure 4.12 input data bus and gram data mapping in 16-bit bus system interface with 18(2+16) bit-data input (tri = 1, dfm = 1 and im3, im2, im1, im0=0010) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.35- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 9-bit parallel bus system interface the i80-system 9-bit parallel bus interface t ype i in command-parameter interface mode can be used by setting external pins im3, im2, im1, im0 pins to 1001. and i80-system 9-bit parallel bus interface type ii in command-parameter interface mode can be used by setting im3, im2, im1, and im0pins to1011. figure 4.15 is the example of type i interface with i80 microcomputer system interface. and figure 4.16 is the example of type ii interface with i80 microcomputer system interface. / HX8347-B 9 db17-9 / 9 mpu nwr_scl nrd ncs db8 -0 dnc_scl figure 4.13: example of i80 system 9-bit parallel bus interface type i / h x8347-b 8 mpu n wr_scl rw_ nrd ncs db17db10 dnc_scl db9 / 8 d b1~db8 db0 figure 4.14: example of i80 system 9-bit parallel bus interface type ii f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.36- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 gram data i nput data bus transfer order 9-bit data 262,144 colors are available r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 1 2 9-bit data db 0 db 0 f igure 4.15: input data bus and gram data mapping in 9-bit bus system interface with 18-bit-data input (im3, im2, im1, im0=1001) gram data i nput data bus transfer order 9-bit data 262,144 colors are available r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 1 2 9-bit data db 9 db 9 f igure 4.16 input data bus and gram data mapping in 9-bit bus system interface with 18 bit-data input (im3, im2, im1, im0=1011) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.37- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 8-bit parallel bus system interface the i80-system 8-bit parallel bus interface t ype i in command-parameter interface mode can be used by setting external pins im3, im2, im1, im0 pins to 0001. and i80-system 8-bit parallel bus interface type ii in command-parameter interface mode can be used by setting im3, im2, im1, and im0pins to0011. figure 4.19 is the example of type i interface with i80 microcomputer system interface. and figure 4.20 is the example of type ii interface with i80 microcomputer system interface. / HX8347-B 8 db17- 8 / 10 mpu nwr_scl nrd ncs db7 -0 dnc_scl figure 4.17: example of i80 system 8-bit parallel bus interface type i figure 4.18: example of i80 system 8-bit parallel bus interface type ii gram data i nput data bus transfer order 8-bit data 65,536 colors are available r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 1 2 8-bit data f igure 4.19: input data bus and gram data mapping in 8-bit bus system interface with 16-bit-data input (tri = 0 and im3, im2, im1, im0=0001) gram data t ransfer order 6-bit data 262,144 colors are available r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 d b7 d b6 d b5 d b4 d b3 d b7 d b6 d b5 d b4 d b3 d b2 d b7 d b6 d b5 d b4 d b3 1 d b2 d b2 3 6-bit data 6-bit data 2 f igure 4.20: input data bus and gram data mapping in 8-bit bus system interface with 18-bit-data input (tri = 1 and im3, im2, im1, im0=0001) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.38- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 gram data i nput data bus transfer order 8-bit data 65,536 colors are available r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 1 2 8-bit data f igure 4.21: input data bus and gram data mapping in 8-bit bus system interface with 16 bit-data input (tri = 0 and im3, im2, im1, im0=0011) gram data t ransfer order 2-bit data 262,144 colors are available r5 r4 b5 b4 b3 b2 b1 b0 db 11 db 15 db 14 db 13 db 12 db 11 1 db 10 db 10 3 8-bit data g1 g0 db 17 db 16 r1 r0 g5 g4 g3 g2 db 15 db 14 db 13 db 12 db 11 db 10 2 8-bit data r3 r2 db 17 db 16 f igure 4.22: input data bus and gram data mapping in 8-bit bus system interface with 18 bit-data input (tri = 1, dfm = 0 and im3, im2, im1, im0=0011) gram data t ransfer order 6-bit data 262,144 colors are available r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 db 17 db 16 db 15 db 14 db 13 db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 1 db 12 db 12 3 6-bit data 6-bit data 2 f igure 4.23: input data bus and gram data mapping in 8-bit bus system interface with 18 bit-data input (tri = 1, dfm = 1 and im3, im2, im1, im0=0011) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.39- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 mcu data color coding for ram data r ead - parallel 8-bit bus interface type i (im3,im2,im1,im0=0001) register db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 command tri dfm x x x x x x x x x x 0 0 1 0 0 0 1 0 22h x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x x r4 r3 r2 r1 r0 g5 g4 g3 0 x x x x x x x x x x x g2 g1 g0 b4 b3 b2 b1 b0 65k-color (1-pixel/ 2-bytes) x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x x r5 r4 r3 r2 r1 r0 x x x x x x x x x x x x g5 g4 g3 g2 g1 g0 x x 1 x x x x x x x x x x x b5 b4 b3 b2 b1 b0 x x 262k-color (1-pixel/ 3bytes) table 4.11: 8-bit parallel interface type i gram read table - parallel 16-bit bus interface type i (im3,im2,im1,im0=0000) register db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 command tri dfm x x x x x x x x x x 0 0 1 0 0 0 1 0 22h x x x x x x x x x x x x x x x x x x dummy read 0 x r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 65k-color x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x x x x x x x x x x dummy read x x r5 r4 r3 r2 r1 r0 x x g5 g4 g3 g2 g1 g0 x x x x b5 b4 b3 b2 b1 b0 x x r5 r4 r3 r2 r1 r0 x x 1 0 x x g5 g4 g3 g2 g1 g0 x x b5 b4 b3 b2 b1 b0 x x 262k-color (2-pixels/ 3bytes) x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x x x x x x x x x x dummy read x x r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 1 1 x x x x x x x x x x x x x x x x b1 b0 262k-color (16+2) table 4.12: 16-bit parallel interface type i gram read table - parallel 9-bit bus interface type i (im3,im2,im1,im0=1001) d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register register command x x x x x x x x x x 0 0 1 0 0 0 1 0 22h x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x r5 r4 r3 r2 r1 r0 g5 g4 g3 read data format x x x x x x x x x g2 g1 g0 b5 b4 b3 b2 b1 b0 262k-color (1-pixel/ 2bytes) table 4.13: 9-bit parallel interface type i gram read table - parallel 18-bit bus interface type i (im3,im2,im1,im0=1000) d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register register command x x x x x x x x x x 0 0 1 0 0 0 1 0 22h x x x x x x x x x x x x x x x x x x dummy read read data format r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 262k-color table 4.14: 18-bit parallel interface type i gram read table f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.40- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 - parallel 8-bits bus interface (im3,im2,im1,im0=0011) db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 command register command 0 0 1 0 0 0 1 0 x x x x x x x x x x 22h db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 color x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x x x x x x x x x x dummy read r5 r4 r3 r2 r1 g5 g4 g3 x x x x x x x x x x read data format g2 g1 g0 b5 b4 b3 b2 b1 x x x x x x x x x x 65k-color table 4.15: 8-bits parallel interface type ii gram read table - parallel 16-bits bus interface (im3,im2,im1,im0=0010) db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 command register command x x x x x x x x x 0 0 1 0 0 0 1 0 x 22h db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 color x x x x x x x x x x x x x x x x x x dummy read read data format r5 r4 r3 r2 r1 g5 g4 g3 x g2 g1 g0 b5 b4 b3 b2 b1 x 65k-color table 4.16: 16-bits parallel interface type ii gram read table - parallel 9-bits bus interface (im3,im2,im1,im0=1011) d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register register command 0 0 1 0 0 0 1 0 x x x x x x x x x x 22h d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 color x x x x x x x x x x x x x x x x x x dummy read x x x x x x x x x x x x x x x x x x dummy read r5 r4 r3 r2 r1 r0 g5 g4 g3 x x x x x x x x x read data format g2 g1 g0 b5 b4 b3 b2 b1 b0 x x x x x x x x x 262k-color (1-pixels/ 2bytes) table 4.17: 9-bits parallel interface type ii gram read table - parallel 18-bits bus interface (im3,im2,im1,im0=1010) d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register register command x x x x x x x x x 0 0 1 0 0 0 1 0 x 22h d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 color x x x x x x x x x x x x x x x x x x dummy read read data format r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 262k-color table 4.18: 18-bits parallel interface type ii gram read table f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.41- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 4.1.3 serial bus system interface the HX8347-B supports three kinds serial bus interface in register-content mode by setting e xternal pins im2, im1,im0 pins to 10x 3-wire 24-bits serial interface and im2, im1,im0 pins to 110 3-wire 9-bits serial interface and im2, im1,im0 pins to 111 4-wire 8-bits serial interface. the serial bus system interface mode is enabled through the chip select line (ncs), and it is accessed via a control consisting of the serial input data (sdi), and the serial transfer clock signal (nwr_scl). 4.1.3.1 3-wire serial interface as the chip select signal (ncs) goes low, the start byte needs to be transferred first. the start b yte is made up of 6-bit bus device identification code; register select (rs) bit and read/write operation (rw) bit. the five upper bits of 6-bit bus device identification code must be set to 01110, and the least significant bit of the identification code must be set as the external pin im0 input as id. the seventh bit (rs) of the start byte determines internal index register or register, gram accessing. rs must be set to 0 when writing data to the index register or reading the status and it must be set to 1 when writing or reading a command or gram data. the read or write operation is selected by the eighth bit (rw) of the start byte. the data is written to the chip when r/w = 0, and read from chip when rw = 1. rs r/w function 0 0 set index register 1 0 writes instruction or gram data 1 1 reads command or gram read table 4.19: the function of rs and r/w bit bus figure 4.24: index register read/write timing in 3-wire serial bus system interface f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.42- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 device id code d15 start e nd ncs sdi sdo (input) (output) scl (i nput) device id code start byte index register set, instructions, ram data write status read, instruction read, ram data read 1 2 7 8 9 1 6 17 18 2 4 25 3 2 start byte instruction 1 u pper byte instruction 1 l ower byte instruction2 u pper byte *the first byte after the start byte is always the upper byte instruction1:execution time s cl sdi (input) (input) start e nd ncs scl ( input) start byte sdi ( input) dummy read 1 status read u pper byte status read l ower byte sdo ( input) note: one byte of the read data after the start byte are invalid. the HX8347-B starts to read the correct status or instruction data from the second byte start e nd ncs start b yte ram read l ower byte note: a ram data read operation follows 5-byte dummy read operations. scl sdi sdo (input) (input) (output) start e nd ncs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 19 rs rw d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dummy re ad 1 dummy re ad 2 dummy re ad 3 dummy re ad 4 dummy re ad 5 ram read upper byte figure 4.25: index register read/write timing in 3-wi re serial bus system interface f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.43- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 device id code start end a aa a ) ) ) ) 16 1616 16- -- -bit data transfer timing format in serial bus interface for gram write bit data transfer timing format in serial bus interface for gram write bit data transfer timing format in serial bus interface for gram write bit data transfer timing format in serial bus interface for gram write ( ( ( ( tri tritri tri= = = = 0 00 0) )) ) "01110" id start byte 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 19 rs rw r g b nwr_scl sdi (1-0)= 00 ( 16 bit, 65 k - r5 r4 r3 r2 r1 g5 g4 g3 g2 g1 g0 b 5 b4 b3 b2 b1 65k colors mapping (16bits to 18bits) r1 g1 b1 r2 g2 b2 r3 g3 b3 frame memory 18- bits ncs device id code start end ncs b b b b ) ) ) ) " 01110" id start byte 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 19 rs rw 26 25 b g r nwr_scl sdi 18 18 18 18- -- -bit data transfer timing format in serial bus interface for gram write bit data transfer timing format in serial bus interface for gram write bit data transfer timing format in serial bus interface for gram write bit data transfer timing format in serial bus interface for gram write ( ( ( ( tri tritri tri= == =1 11 1) )) ) 16 bit, 65 k r3 r2 r1 r0 g 5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 r 4r5 r1 g1 b1 r2 g2 b2 r3 g3 b3 18- bits frame memory f igure 4.26: data write timing in 3-wire serial bus system interface 4.1.3.2 4-wire serial interface 4-pin serial case, data packet contains just transmission byte and control bit dnc is transferred b y dnc_scl pin. if dnc_scl is low, the transmission byte is command byte. if dnc_scl is high, the transmission byte is stored to index register or gram. the msb is transmitted first. the serial interface is initialized when ncs is high. in this state, nwr_scl clock pulse or sdi data have no effect. a falling edge on ncs enables the serial interface and indicates the start of data transmission. ncs nwr_scl sdi 4 44 4- -- -wire serial peripheral interface protocol wire serial peripheral interface protocol wire serial peripheral interface protocol wire serial peripheral interface protocol command ncs can be "h" between command and parameter parameter d0d1d2d3d4d5d6d7 d1 d0 d2 d3d4 d5 d6 d7 dnc_scl figure 4.27: index register write timing in 4-wire serial bus system interface f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.44- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 16-bit 65k data mapping (16-bit to 18 bit) r1 g1 b1 r2 g2 b2 18-bit gram r1 2 r1 0 r1 1 b1 0 b1 1 nwr_scl sdi b1 2 b1 3 r1 3 g1 2 g1 0 g1 1 g1 3 b1 4 g1 5 g1 4 r1 4 16 1616 16- -- -bit data transfer timing format in bit data transfer timing format in bit data transfer timing format in bit data transfer timing format in 4 44 4- -- -wire serial bus interface for gram write wire serial bus interface for gram write wire serial bus interface for gram write wire serial bus interface for gram write ( ( ( ( tri tritri tri= == =0 00 0) )) ) figure 4.28: data write timing in 4-wire serial bus system interface 4.1.3.3 3-wire serial interface serial data must be input to s da in the sequence d/nc, d7 to d0. the HX8347-B reads the sda data at the rising edge of scl signal. the first bit of serial data d/nc is data/command flag. when d/nc = "1", d7 to d0 bits are gram data or command parameters. when d/nc = "0" d7 to d0 bits are commands. scl is not a continuous clock and it can be stopped by the host mcu when scl is low or high after a rising edge of scl for d0 in the writing mode. msb l sb when d/nc = "0", transmission byte (tb) must be a command when d/nc = "1", transmission byte (tb) must be a command parameters or gram data 3-wire serial peripheral interface data format d/nc d7 d6 d5 d4 d3 d2 d1 d0 d/nc tb tb tb d/nc d/nc tb f igure 4.29: serial peripheral interface data format f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.45- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 write operation in serial peripheral interface the host mcu drives the n cs pin low and starts by setting the d/cx-bit on sda . the bit is read by the display on the first rising edge of scl . on the next falling edge of scl the msb data bit (d7) is set on sda by the mcu. on the next falling edge of scl the next bit (d6) is set on sda . this continues until all 8 data bits have been transmitted as shown in figure 4.30 and figure 4.31. ncs scl tb s sda 0 d_nc tb p 3-wire serial peripheral interface protocol command ncs can be "h" between command and parameter command / parameter d0d1d2d3d4d5d6d7 d/nc d1 d0 d2 d3 d4d5 d6 d7 f igure 4.30: serial peripheral interface protocol in command write operation ncs scl tb s sda 0 d_nc tb p 3-wire serial peripheral interface protocol command ncs can be "h" between command and parameter gram data d0d1d2d3d4d5d6d7 1 0 0 1 1 01 0 0 f igure 4.31: serial peripheral interface protocol in gram write operation f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.46- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 read operation in serial peripheral interface when users need to read back the register or gram data, the register r66h must be set as 1 f irst, and then write the register index to read back the register or gram data. the following timing diagrams show examples to read back the register data. figure 4.32: command read operation in serial peripheral interface f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.47- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 there are two types data format to write display data at serial data bus interface and it is as sa me as 8-bit bus interface. f igure 4.33: write data for rgb 5-6-5-bits (65k colors) input (tri=0) figure 4.34: write data for rgb 6-6-6-bits(262k colors) (tri=1) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.48- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 4.2 vsync interface the HX8347-B supports the vsync interface mode that executes the display operation by the i nternal clocks. the internal clocks is generated from internal oscillators and synchronized with the frame synchronization signal vsync. when the vsync interface mode is selected, the interface display a moving picture through system interface with minimum modification that re-writes display data to the internal gram in a high speed ram function. the vsync interface can be used by setting dm1-0=10 and rm=0. figure 4.35: vsync interface to mpu dm1 dm0 operation mode 0 0 system interface 0 1 rgb interface 1 0 vsync interface 1 1 ignore table 4.20: dim bit set when the HX8347-B is set up in vsync interface mode, the interface is used to display a m oving picture when writing data to gram in high speed with low power consumption. therefore, the vsync interface has some constraints in the internal clock and the ram write speed via the system interface. it requires gram write speed more than the minimum value that system processed and calculated. the internal clock of vsync interfaces can be computed by the following formula that used some parameters with fp, bp and display lines duration (nl): [ ] nfluctuatio frequency rtnbpfpnllines display frequency frame hzfclock ocillator internal osc ++ = ])( [ )( the parameter of frequency fluctuation is ascribed to the external resistor or voltage variation, f abrication process condition, external temperature and humidity condition etc. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.49- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 the minimum speed for ram can be computed by the following formula: rtnlinesinmnlsdisplyline bpochback fnles displaylin hzspeedwriteramminthe osc - + ]arg)( )(pr[ )( 240 ][ . R the margin line means when operate in vsync interface mode, it must be remained the se veral lines in advance for protection between the actual line of the display operation and the line address for the ram write data operation. the calculated value is the theoretical value that the HX8347-B start the ram write operation must be taken into account. in other words, the actual value of ram write speed must be more than theoretical value that calculated from forward formula by getting an internal oscillator clock (fosc) first. an example of internal oscillator clock (fosc) and minimum speed for ram writing set up in vsync interface mode is as follows. example d isplay size: 240rgb*320 lines lines of be used: 320 lines fp: 2 lines (0010) bp: 14 lines (1110) frequency fluctuation: 5 R RR R in this example, the minimum ram write speed of vsync interface is 5.11mhz and then necessary to setting enough or more on the falling edge of guarantees the completion write operation before the HX8347-B initiate the display operation and make it possible to re-write the display area set previously. further, if the display area were different with the anterior example, the calculated result and margin setting would be revised. for example, if the display area is smaller than that, an extra will be created between the ram write operation and display with regard to each line. when the HX8347-B make the transition with system interface mode and vsync interface mode, the difference between that is the used of signal vsync for synchronization. therefore, both of them are used the internal oscillator to generate the reference clock. the figure 4.36 illustrates the process of vsnc interface with internal clock and system interface with internal clock mode transition, which is shown by setting register set. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.50- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 figure 4.36: vsync interface with internal clock and system interface with internal clock mode transition when HX8347-B is set up on vsync interface mode, it would access ram in high speed with l ow power consumption for displaying a moving picture. but the partial display function, vertical scroll function and interlaced scan function are invalidity functions in vsync interface mode. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.51- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.3 rgb interface the HX8347-B supports the rgb interface that display operations that executed in sy nchronization with the frame synchronizing signal (vsync), line synchronizing signal (hsync) and dot clock (dotclk). the display data are transferred in pixel unit via db17-0 bits. the rgb interface can be used by setting dm[1:0]=01 and rm = 1 . in rgb interface mode, with use of a window address function, enables to display data in a moving picture area and makes it possible to transfer the display only by re-writing a screen with minimum data transfers. when the HX8347-B set up in rgb interface mode, a bp starts on the falling edge of vsync si gnal, which is made at the beginning by the display operation. furthermore, the display duration (nl4-0) mean the numbers of driving lines is the subsequent data of display operation. and then the fp starts. the fp period would be continues until the next input of the vsync signal. general timing diagram in rgb interface is as follow: figure 4.37: rgb interface circuit input timing diagram t he data written to the internal gram were synchronized with dotclk inputs when de is setting low. contrary to set de high, the data written to the gram would be entered to the process of using the system interface. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.52- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 moving picture mode HX8347-B has the rgb interface to display moving picture and incorporates gram to store d isplay data. the figure 4.38 is shown the process of ram access via the system interface with rewriting still picture and then return to rgb interface while displaying a moving picture in rgb interface mode. figure 4.38: example of update still and moving picture when set up in rgb interface mode, the used of high speed ram write mode to write data to t he internal gram and gram address (ad15-0) is set in the address counter for every frame on the falling edge of vsync. furthermore, the fp period would be continues until the next input of the vsync signal. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.53- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 when the HX8347-B make the transition with system interface mode and rgb interface m ode, the sequence of switching process must be following as figure 4.39. system interface mode to rgb interface mode s ystem interface mode set ad15-0 set rgb interface mode* (dm1-0=01, rm=1) set ir to r22h (ram data write) wait more than 1 frame write data through rgb interface rgb interface operation rgb interface mode to system interface mode set system interface mode (dm1-0=00, rm=0) wait more than 1 frame rgb interface mode rgb interface operation system interface mode * dm1-0, rm settings become enabled after compretion of displaying one frame (synchronized with vsync, hsync, dotclk) rgb interface operation (synchronized with vsync, hsync, dotclk) * dm1-0, rm settings become enabled after compretion of displaying one frame system interface mode figure 4.39: transition between system interface mode and rgb interface mode f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.54- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 when operate in rgb interface and the ram write data transfer through system interface, the se quence of switching process must be follow as figure 4.40. figure 4.40: ram data write sequence through system interface or rgb interface during rgb interface mode f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.55- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 the HX8347-B supports 18-/16-/6-bit bus rgb interface by setting register rim1-0 only t hrough the system interface. rim[1:0] d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bus width 0 0 r4 r3 r2 r1 r0 x g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 x 16-bits data 0 1 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 18-bits data x x x x x x x x x x r5 r4 r3 r2 r1 r0 x x x x x x x x x x x x g5 g4 g3 g2 g1 g0 x x 1 0 x x x x x x x x x x b5 b4 b3 b2 b1 b0 x x 6-bits data 18-bit bus rgb interface input ram data write r5 r4 r 3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 262 , 144 colors available in18- bit rgb interface. write data to gram pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd 16 15 14 13 11 10 9 8 7 6 5 4 3 2 1 17 0 12 figure 4.41: data format for 18-bit interface 16-bit bus rgb interface input ram data write pd 17 16 15 14 13 11 10 9 8 7 6 5 4 3 2 r5 r4 r3 r2 r1 r 0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 1 gram write data pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd figure 4.42: data format for16-bit interface 6-bit bus rgb interface ram data write input gram write data pd 17 pd 16 pd 15 pd 14 pd 13 pd 12 pd 17 pd 16 pd 15 pd 14 pd 13 pd 12 pd 17 pd 16 pd 15 pd 14 pd 13 pd 12 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 262,144 colors are available in 6-bit system interface. 1st transfer 2nd transfer 3rd transfer figure 4.43: data format for 6-bit interface f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.56- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5. functional description 5.1 display data gram mapping the display data ram stores display dots and consists of 1,382,400 bits (240x18x320 bits). t here is no restriction on access to the ram even when the display data on the same address is loaded to dac. there will be no abnormal visible effect on the display when there is a simultaneous panel read and interface read or write to the same location of the frame memory. every pixel (18-bit) data in gram is located by a (page, column) address (y, x). by specifying the arbitrary window address sc, ec bits and sp, ep bits, it is possible to access the gram by setting ramwr or ramrd commands from start positions of the window address. (00,00)h (00,01)h (00,02)h --------- (00,ec)h (00,ed)h (00,ee)h (00,ef)h (01,00)h (01,01)h (01,02)h --------- (01,ec)h (01,ed)h (01,ee)h (01,ef)h (02,00)h (02,01)h (02,02)h --------- (02,ec)h (02,ed)h (02,ee)h (02,ef)h (03,00)h (03,01)h (03,02)h --------- (03,ec)h (03,ed)h (03,ee)h (03,ef)h (04,00)h (04,01)h (04,02)h --------- (04,ec)h (04,ed)h (04,ee)h (04,ef)h (05,00)h (05,01)h (05,02)h --------- (05,ec)h (05,ed)h (05,ee)h (05,ef)h -------- -------- -------- --------- -------- -------- -------- -------- (13a,00)h (13a,01)h (13a,02)h --------- (13a,ec)h (13a,ed)h (13a,ee)h (13a,ef)h (13b,00)h (13b,01)h (13b,02)h --------- (13b,ec)h (13b,ed)h (13b,ee)h (13b,ef)h (13c,00)h (13c,01)h (13c,02)h --------- (13c,ec)h (13c,ed)h (13c,ee)h (13c,ef)h (13d,00)h (13d,01)h (13d,02)h --------- (13d,ec)h (13ded)h (13d17e)h (13d,ef)h (13e,00)h (13e,01)h (13e,02)h --------- (13e,ec)h (13e,ed)h (13e,ee)h (13e,ef)h (13f,00)h (13f,01)h (13f,02)h --------- (13f,ec)h (13f,ed)h (13f,ee)h (13f,ef)h table 5.1: gram address for display panel position f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.57- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.2 gram to display address mapping by setting the s s , the relation between the source output channel and the gram address can be changed as reverse display. by setting the gs , the relation between the gate output channel and the gram address can be changed as reverse display. by setting the bgr , the relation between the source output channel and the -p.58- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 s/g pins s1 s2 s3 s4 s5 s6 s7 s8 s9 --------- s709 s710 s711 s712 s713 s714 s715 s716 s717 s718 s719 s720 g1 0000h 0001h 0002h --------- 00ech 00edh 00eeh 00efh g2 0100h 0101h 0102h --------- 01ech 01edh 01eeh 01efh g3 0200h 0201h 0202h --------- 02ech 02edh 02eeh 02efh g4 0300h 0301h 0302h --------- 03ech 03edh 03eeh 03efh g5 0400h 0401h 0402h --------- 04ech 04edh 04eeh 04efh g6 0500h 0501h 0502h --------- 05ech 05edh 05eeh 05efh g7 0600h 0601h 0602h --------- 06ech 06edh 06eeh 06efh g8 0700h 0701h 0702h --------- 07ech 07edh 07eeh 07efh g9 0800h 0801h 0802h --------- 08ech 08edh 08eeh 08efh ------- ------- ------- ------- --------- ------- ------- ------- ------- g311 13600h 13601h 13602h --------- 136ech 136edh 136eeh 136efh g312 13700h 13701h 13702h --------- 137ech 137edh 137eeh 137efh g313 13800h 13801h 13802h --------- 138ech 138edh 138eeh 138efh g314 13900h 13901h 13902h --------- 139ech 139edh 139eeh 139efh g315 13a00h 13a01h 13a02h --------- 13aech 13aedh 13aeeh 13aefh g316 13b00h 13b01h 13b02h --------- 13bech 13bedh 13beeh 13befh g317 13c00h 13c01h 13c02h --------- 13cech 13cedh 13ceeh 13cefh g318 13d00h 13d01h 13d02h --------- 13dech 13dedh 13deeh 13defh g319 13e00h 13e01h 13e02h --------- 13eech 13eedh 13eeeh 13eefh g320 13f00h 13f01h 13f02h --------- 13fech 13fedh 13feeh 13fefh table 5.3: gram address and display panel position (gs =0) s/g pins s1 s2 s3 s4 s5 s6 s7 s8 s9 --------- s709 s710 s711 s712 s713 s714 s715 s716 s717 s718 s719 s720 g320 0000h 0001h 0002h --------- 00ech 00edh 00eeh 00efh g319 0100h 0101h 0102h --------- 01ech 01edh 01eeh 01efh g318 0200h 0201h 0202h --------- 02ech 02edh 02eeh 02efh g317 0300h 0301h 0302h --------- 03ech 03edh 03eeh 03efh g316 0400h 0401h 0402h --------- 04ech 04edh 04eeh 04efh g315 0500h 0501h 0502h --------- 05ech 05edh 05eeh 05efh g314 0600h 0601h 0602h --------- 06ech 06edh 06eeh 06efh g313 0700h 0701h 0702h --------- 07ech 07edh 07eeh 07efh g312 0800h 0801h 0802h --------- 08ech 08edh 08eeh 08efh ------- ------- ------- ------- --------- ------- ------- ------- ------- g10 13600h 13601h 13602h --------- 136ech 136edh 136eeh 136efh g9 13700h 13701h 13702h --------- 137ech 137edh 137eeh 137efh g8 13800h 13801h 13802h --------- 138ech 138edh 138eeh 138efh g7 13900h 13901h 13902h --------- 139ech 139edh 139eeh 139efh g6 13a00h 13a01h 13a02h --------- 13aech 13aedh 13aeeh 13aefh g5 13b00h 13b01h 13b02h --------- 13bech 13bedh 13beeh 13befh g4 13c00h 13c01h 13c02h --------- 13cech 13cedh 13ceeh 13cefh g3 13d00h 13d01h 13d02h --------- 13dech 13dedh 13deeh 13defh g2 13e00h 13e01h 13e02h --------- 13eech 13eedh 13eeeh 13eefh g1 13f00h 13f01h 13f02h --------- 13fech 13fedh 13feeh 13fefh table 5.4: gram address and display panel position (gs =0) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.59- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.3 window address function t he HX8347-B contains a gram address counter (ac), which assigns address for writing pixel data to gram. every time when a pixel data is written into the gram, the x address or y address of ac will be automatically increased by 1 (or decreased by 1), which is decided by the register (am bit and i/d bits) setting. however, the ac will be not updated after reading from gram. to simplify the address control of gram access, the window address function allows for writing data only to a window area of gram specified by registers. after data being written to the gram, the ac will be increased or decreased within setting window address-range which is specified by the horizontal address register (start: hsa, end: hea) or the vertical address register (start: vsa, end: vea). therefore, data can be written consecutively without thinking a data wrap by those bit function. the address setting of window and gram are listed as following: the window addresses setting range: 0 0h has Q QQ Q [7:0] hea Q QQ Q [7:0] Q QQ Q efh 000h vsa Q QQ Q [8:0] vea Q QQ Q [8:0] Q QQ Q 13fh gram address setting range: has[7:0] ad Q QQ Q [7:0] hea Q QQ Q [7:0] vsa[8:0] ad Q QQ Q [16:8] vea Q QQ Q [8:0] gram address map 00000h 000efh 13fefh 13f00h window address area 02010h 02110h 0203fh 0213fh 04f10h 04f3fh window address setting area hsa[7:0]=10h,hea[7:0]=3fh vsa[8:0]=20h,vea[8:0]=4fh i/d=1 (increment),am=0 (horizontal writing) figure 5.1: gram window address mapping example f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.60- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.4 tearing effect output line the tearing effect output line supplies to the mpu a panel synchronization signal. this signal ca n be enabled or disabled by the tearing effect line off & on commands. the mode of the tearing effect signal is defined by the parameter of the tearing effect line on command. the signal can be used by the mpu to synchronize frame memory writing when displaying video images. tearing effect function is not support when at rgb interface. 5.4.1 tearing effect line modes mode 1 , the tearing effect output signal consists of back porch information only: t vdh = the lcd display is not updated from the frame memory t vdl = the lcd display is updated from the frame memory (except invisible line C see below) figure 5.2: te mode 1 output under mode1, the te output timing will be defined by tep[8:0] setting. e x: a. tep[8:0]=0, then te signal will output after last line finished. b. tep[8:0]=2, then te signal will output at second line start. figure 5.3: te delay output f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.61- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 mode 2 , the tearing effect output signal consists of v-blanking and h-blanking information, there is one v-sync and 320 h-sync pulses per field. t hdh = the lcd display is not updated from the frame memory t hdl = the lcd display is updated from the frame memory (except invisible line C see above) f igure 5.4: te mode 2 output note: d uring sleep in mode, the tearing output pin is active low figure 5.5: te output waveform f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.62- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.4.2 tearing effect line timing the tearing effect signal is described below. figure 5.6: waveform of tearing effect signal idle mode off (frame rate = 60 hz) symbol parameter min. max. unit description tvdl vertical timing low duration tbd - ms - tvdh vertical timing high duration tbd - us - thdl horizontal timing low duration tbd - us - thdh horizontal timing high duration tbd 500 us - table 5.5: ac characteristics of tearing effect signal t he signals rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. figure 5.7: timing of tearing effect signal the tearing effect output line is fed back to the mpu and should be used as shown below to a void tearing effect: f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.63- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.4.3 example 1: mpu write is faster than panel read time t ime time mcu to memory te output signal memory to lcd image on lcd a b c d 1st 320th 1st 320th figure 5.8: timing of mpu write is faster than panel read data write to frame memory is now synchronized to the panel scan. it should be written d uring the vertical sync pulse of the tearing effect output line. this ensures that data is always written ahead of the panel scan and each panel frame refresh has a complete new image. figure 5.9: display of mpu write is faster than panel read f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.64- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.4.4 example 2: mpu write is slower than panel read time t ime time mcu to memory te output signal memory to lcd image on lcd a b c d 1st 320th 1 st 3 20th e f figure 5.10: timing of mpu write is slower than panel read t he mpu to frame memory write begins just after panel read has commenced i.e. after one horizontal sync pulse of the tearing effect output line. this allows time for the image to download behind the panel read pointer and finishing download during the subsequent frame before the read pointer catches the mpu to frame memory write position. figure 5.11: display of mpu write is slower than panel read f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.65- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.5 internal oscillator the HX8347-B can oscillate an internal r-c oscillator for internal operation. because the t olerance of internal oscillator frequency is 5%, frs [3:0] bits for initial 2.85mhz internal cl ock generation. with other dividers setting, the 2.85mhz internal clock can be used to generate clock for other part of the chip using. internal display mode internal display mode internal display mode internal display mode fosc foscfosc fosc rgb display mode rgb display mode rgb display mode rgb display mode oscillator oscillatoroscillator oscillator clock clockclock clock dotclk d otclkdotclk dotclk frequency frequency frequency frequency divider divider divider divider 1 11 1 dc dcdc dc0 00 0[ [[ [2 22 2: :: :0 00 0] ]] ] for ddvdh for ddvdh for ddvdh for ddvdh, , , , vcl vclvcl vcl divi dividivi divi[ [[ [1 11 1: :: :0 00 0] ]] ] pwm pwmpwm pwm_ __ _clk clk clk clk ( (( (for backlight cabc for backlight cabc for backlight cabc for backlight cabc) )) ) 2 22 2. .. .85 8585 85mhz mhzmhz mhz frequency frequency frequency frequency divider divider divider divider 2 22 2 dc dcdc dc1 11 1[ [[ [2 22 2: :: :0 00 0] ]] ] for vgh for vghfor vgh for vgh, ,, ,vgl vglvgl vgl display displaydisplay display controller controllercontroller controller frs frsfrs frs[ [[ [3 33 3: :: :0 00 0] ]] ] dotclk dotclkdotclk dotclk rgb display mode rgb display mode rgb display mode rgb display mode figure 5.12: HX8347-B internal clock circuit 5.6 source driver the HX8347-B contains a 720 channels of source driver (s1~s720) which is used for driving t he source line of tft lcd panel. the source driver converts the digital data from gram into the analog voltage for 720 channels and generates corresponding gray scale voltage output, which can realize a 262k colors display simultaneously. since the output circuit of this source driver incorporates an operational amplifier, a positive and a negative voltage can be alternately outputted from each channel. 5.7 gate driver the HX8347-B contains a 320 gate channels of gate driver (g1~g320) which is used for d riving the gate. the gate driver level is vgh when scan some line, vgl the other lines. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.66- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.8 scan mode setting h x8347-b can set register gs and sm bit to determine the pin assignment of gate. the combination of sm and gs settings allows changing the shift direction of gate outputs by connecting lcd panel with the HX8347-B. g320 g 319 g2 g1 HX8347-B tft panel g1, g2, g3, g4,.... g317, g318, g319, g320 g318 g4 g317 g3 g2 to g320 g1 to g319 0 0 sm gs scan direction 0 1 1 0 1 1 o dd- number line even- number line g320 g 319 g2 g1 HX8347-B tft panel g320, g319, g318, g317,.... g4, g3, g2, g1 g318 g4 g317 g3 g2 to g320 g1 to g319 odd- number line even- number line g320 g 319 g2 g1 HX8347-B tft panel g320, g318, g316, g314,.... g6, g4, g2 g2 to g320 g1 to g319 odd- number line even- number line g320 g 319 g2 g1 HX8347-B tft panel g1, g3, g5,.... g315, g317, g319, g320 g2 to g320 g1 to g319 odd- number line even- number line g2, g4, g6,.... g 314, g316, g318, g320 g319, g317, g315, g313,.... g 5, g3, g1 figure 5.13: gate scan mode f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.67- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.9 lcd power generation circuit 5.9.1 power supply circuit the power circuit of HX8347-B is used to generate supply voltages for lcd panel driving. step up circuit 1 c11p c11n ddvdh step up circuit 3 vcl c cc c3 33 3 c cc c1 11 1 c cc c9 99 9 reference voltage generation circuit c12p c12n c cc c2 22 2 vreg1 step up circuit 2 c21n c21p c cc c4 44 4 c22p c22n c cc c5 55 5 vgh c cc c6 66 6 vgl c cc c7 77 7 c31p c31n c cc c8 88 8 vddd reference voltage generation circuit reference voltage generation circuit vci vcivci vci vssa vssavssa vssa vssd vssdvssd vssd ddvdh c cc c10 1010 10 figure 5.14: the block diagram of HX8347-B power circuit f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.68- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 specification of connected passive component capacitor recommended voltage capacity c1 (c11p/n) 6v 1f (b characteristics) c2 (c12p/n) 6v 1f (b characteristics) c3 (ddvdh) 10v 1f (b characteristics) c4 (c21p/n) 10v 1f (b characteristics) c5 (c22p/n) 10v 1f (b characteristics) c6 (vgh) 25v 1f (b characteristics) c7 (vgl) 16v 1f (b characteristics) c8 (c31p/n) 6v 1f (b characteristics) c9 (vcl) 6v 1f (b characteristics) c10 (vddd) 6v 1f (b characteristics) table 5.6: the adoptability of capacitor f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.69- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.9.2 lcd power generation scheme the boost voltage generated is shown as below. vssa, vssd (0v) vr eg1 (3.3v ~5.8v) vcomh vgh(2ddvdh~3ddvdh) vcoml vcl vgh vci (2.5 ~ 3.3v) ddvdh d dvdh vgl(-vci-2ddvdh~ -v ci-ddvdh) dc/dc dc/dc dc/dc dc/dc vgl v coml vcomh vreg1 vddd iovcc (1.65 ~ 3.3v) figure 5.15: lcd power generation scheme f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.70- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.10 gamma characteristic correction function the HX8347-B incorporates gamma adjustment function for the 262,144-color display (64 g rayscale for each r, g, b color). gamma adjustment operation is implemented by deciding the 8 grayscale levels firstly in gamma adjustment control registers to match the lcd panel. then total 64 grayscale levels are generated in grayscale voltage generator. these registers are available for both polarities. grayscale voltage generator 6-bit grayscale d/a converter output driver output driver output driver 6-bit grayscale d/a converter 6-bit grayscale d/a converter r g b lcd v0 v1 v63 graphics ram (gram) 6 02 01 00 12 11 01 00 10 12 11 op 14 op 13 03 04 positive polarity register op op op op op op op 02 01 00 12 11 10 22 21 20 32 31 30 42 41 40 52 51 50 10 mp mp mp mp mp mp mp mp mp cp cp cp cp cp cp mp mp mp mp mp mp mp mp mp negative polarity registre 02 01 00 12 11 10 01 00 10 12 11 on 14 02 mn mn mn mn mn mn cn cn on on mn mn mn mn mn mn cn cn on on mn mn mn mn mn mn cn cn on on on on 02 01 00 12 11 10 22 21 20 32 31 30 42 41 40 52 51 50 13 03 6 6 b 3 b 2 b 1 b 0 g 5 g 3 g 2 g 1 g 0 g 4 b 5 b 4 r 5 r 3 r 2 r 1 r 0 r 4 figure 5.16: grayscale control f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.71- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 structure of grayscale voltage generator e ight reference gamma voltages vgp/n(0, 1, 8, 20, 43, 55, 62, 63) for positive and negative polarity are specified by the center adjustment, the micro adjustment and the offset adjustment registers firstly. with those eight voltages injected into specified node of grayscale voltage generator, total 64 grayscale voltages (v0-v63) can be generated from grayscale amplifier for lcd panel used. vgs vgam1out 3 3 5 5 gray scale voltage generator micro adjust register (6* 3 bits) 8 to 1 select 333333 mp/n5 mp/n4 mp/n3 mp/n2 mp/n1 mp/n0 vgp1/vgn1 vgp8/vgn8 vgp20/vgn20 vgp43/vgn43 vgp55/vgn55 vgp62/vgn62 vgp0/vgn0 vgp63/vgn63 8 to 1 select 8 to 1 select 8 to 1 select 8 to 1 select 8 to 1 select v0 v1 v2 v3 v8 v9 v20 v21 v43 v44 v55 v56 v57 v62 v63 gamma resister stream cp/n1 cp/n0 center adjust register op/n1 op/n0 offset adjust register figure 5.17: structure of grayscale voltage generator f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.72- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 gamma-characteristics adjustment register t his HX8347-B has register groups for specifying a series grayscale voltage that meets the gamma-characteristics for the lcd panel used. these registers are divided into two groups, which correspond to the gradient, amplitude, and macro adjustment of the voltage for the grayscale characteristics. the polarity of each register can be specified independently. (r, g, and b are common.) a. offset adjustment registers 0/1 the offset adjustment variable registers are used to adjust the amplitude of the grayscale voltage. this function is implemented by controlling these variable resisters in the top and bottom of the gamma resister stream for reference gamma voltage generation. these registers are available for both positive and negative polarities b. gamma center adjustment registers the gamma center adjustment registers are used to adjust the reference gamma voltage in the middle level of grayscale without changing the dynamic range. this function is implemented by choosing one input of 8 to 1 selector in the gamma resister stream for reference gamma voltage generation. these registers are available for both positive and negative polarities. c. gamma macro adjustment registers the gamma macro adjustment registers can be used for fine adjustment of the reference gamma voltage. this function is implemented by controlling the 8-to-1 selectors (mp/n0~5), each of which has 8 inputs and generate one reference voltage output (vgp/n) 1, 8, 20, 43, 55, 62). these registers are available for both positive and negative polarities. register groups positive polarity negative polarity description cp0 2-0 cn0 2-0 variable resistor (vrcp/n0) for center adjustment center adjustment cp1 2-0 cn1 2-0 variable resistor (vrcp/n1) for center adjustment mp0 2-0 mn0 2-0 8-to-1 selector (voltage level of grayscale 1) mp1 2-0 mn1 2-0 8-to-1 selector (voltage level of grayscale 8) mp2 2-0 mn2 2-0 8-to-1 selector (voltage level of grayscale 20) mp3 2-0 mn3 2-0 8-to-1 selector (voltage level of grayscale 43) mp4 2-0 mn4 2-0 8-to-1 selector (voltage level of grayscale 55) macro adjustment mp5 2-0 mn5 2-0 8-to-1 selector (voltage level of grayscale 62) op0 3-0 on0 3-0 variable resistor (vrop/n0) for offset adjustment offset adjustment op1 4-0 on1 4-0 variable resistor (vrop/n1) for offset adjustment table 5.7: gamma-adjustment registers f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.73- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 gamma resister stream and 8 to 1 selector t he block consists of two gamma resister streams one is for positive polarity and the other is for negative polarity, each one including eight gamma reference voltages. (vgp/n) 0, 1, 8, 20, 43, 55, 62, 63). furthermore, the block has pin (vgs) to connect a variable resistor outside the chip for the variation between panels if needed. { { { { { { exvr { { { { { { vgs v0 v0 8 to 1 select vn2 vn3 vn4 vn5 vn6 vn7 vn8 vn1 8 to 1 select vn10 vn11 vn12 vn13 vn14 vn15 vn16 vn9 8 to 1 select vn18 vn19 vn20 vn21 vn22 vn23 vn24 vn17 8 to 1 select vn26 vn27 vp28 vn29 vn30 vn31 vn32 vn25 8 to 1 select vn34 vn35 vn36 vn37 vn38 vn39 vn40 vn33 8 to 1 select vn42 vn43 vn44 vn45 vn46 vn47 vn48 vn41 rn1 rn2 rn3 rn4 rn5 rn6 rn7 rn8 rn9 rn10 rn11 rn12 rn13 rn14 rn16 rn17 rn18 rn19 rn20 rn21 rn22 rn24 rn25 rn26 rn27 rn28 rn29 rn30 rn32 rn33 rn34 rn35 rn36 rn37 rn38 rn39 rn40 rn41 rn42 rn43 rn44 rn45 cn0[2:0] 5r vgn1 8r rn15 rn23 rn31 rn46 rn0 vron1 0 ~ 31r vn49 rn47 mn0[2:0] mn1[2:0] vgn8 mn2[2:0] vgn20 mn3[2:0] vgn43 mn4[2:0] vgn55 cn1[2:0] vgn62 mn5[2:0] on1[4:0] vgn63 on0[3:0] vgn0 4r 1r 1r 1r 1r 4r 16r 5r 5r 5r vrcn0 0 ~2 8r vrcn1 0 ~2 8r vron0 0 ~ 30r 8 to 1 select 8 to 1 select 8 to 1 select 8 to 1 select 8 to 1 select 8 to 1 select cp0[2:0] vgp1 mp0[2:0] mp1[2:0] vgp8 mp2[2:0] vgp20 mp3[2:0] vgp43 mp4[2:0] vgp55 cp1[2:0] vgp62 mp5[2:0] vgp63 op1[4:0] op0[3:0] vgp0 vp2 vp3 vp4 vp5 vp6 vp7 vp8 vp1 vp10 vp11 vp12 vp13 vp14 vp15 vp16 vp9 vp18 vp19 vp20 vp21 vp22 vp23 vp24 vp17 vp26 vp27 vp28 vp29 vp30 vp31 vp32 vp25 vp34 vp35 vp36 vp37 vp38 vp39 vp40 vp33 vp42 vp43 vp44 vp45 vp46 vp47 vp48 vp41 rp1 rp2 rp3 rp4 rp5 rp6 rp7 rp8 rp9 rp10 rp11 rp12 rp13 rp14 rp16 rp17 rp18 rp19 rp20 rp21 rp22 rp24 rp25 rp26 rp27 rp28 rp29 rp30 rp32 rp33 rp34 rp35 rp36 rp37 rp38 rp39 rp40 rp41 rp42 rp43 rp44 rp45 4r 1r 1r 1r 1r 4r 16r 5r 5r 5r 8r rp15 rp23 rp31 rp46 5r rp0 vrcp0 0 ~2 8r vrcp1 0 ~2 8r vrop1 0 ~ 31r vp49 rp47 vgam1out vrop0 0 ~ 30r f igure 5.18: gamma resister stream and gamma reference voltage f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.74- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 variable resister t here are two types of variable resistors, one is for center adjustment, and the other is for offset adjustment. the resistances are decided by setting values in the center adjustment, offset adjustment registers. their relationships are shown below. value in register o(p/n)0 3-0 resistance vro(p/n)0 value in register o(p/n)1 4-0 resistance vro(p/n)1 value in register c(p/n)0/1 2-0 resistance vrc(p/n)1 0000 0r 00000 0r 000 0r 0001 2r 00001 1r 001 4r 0010 4r 00010 2r 010 8r 011 12r 100 16r 1101 26r 11101 29r 101 20r 1110 28r 11110 30r 110 24r 1111 30r 11111 31r 111 28r table 5.8: offset adjustment 0 table 5.9: offset adjustment 1 table 5.10: center adjustment 8 to 1 selector the 8 to 1 selector has eight input voltages generated by gamma resister stream. it outputs o ne reference voltages selected from inputs for gamma reference voltage generation by setting value in macro adjustment register. these six 8 to 1 selectors and the relationship are shown below. value in register voltage level m(p/n) 2-0 vg(p/n) 1 vg(p/n) 8 vg(p/n) 20 vg(p/n) 43 v(p/n) 55 v(p/n) 62 000 vp(n)1 vp(n)9 vp(n)17 vp(n)25 vp(n)33 vp(n)41 001 vp(n)2 vp(n)10 vp(n)18 vp(n)26 vp(n)34 vp(n)42 010 vp(n)3 vp(n)11 vp(n)19 vp(n)27 vp(n)35 vp(n)43 011 vp(n)4 vp(n)12 vp(n)20 vp(n)28 vp(n)36 vp(n)44 100 vp(n)5 vp(n)13 vp(n)21 vp(n)29 vp(n)37 vp(n)45 101 vp(n)6 vp(n)14 vp(n)22 vp(n)30 vp(n)38 vp(n)46 110 vp(n)7 vp(n)15 vp(n)23 vp(n)31 vp(n)39 vp(n)47 111 vp(n)8 vp(n)16 vp(n)24 vp(n)32 vp(n)40 vp(n)48 table 5.11: output voltage of 8 to 1 selector f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.75- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 the grayscale levels are determined by the following formulas reference voltage macro adjustment value formula pin vgp0 - vreg1out-vd*vrop0 /sumrp vp0 mp0 2-0=000 vreg1out -vd((vrop0+5r) /sumrp vp1 mp0 2-0=001 vreg1out -vd((vrop0+9r) /sumrp vp2 mp0 2-0=010 vreg1out -vd((vrop0+13r) /sumrp vp3 mp0 2-0=011 vreg1out -vd((vrop0+17r) /sumrp vp4 mp0 2-0=100 vreg1out -vd((vrop0+21r) /sumrp vp5 mp0 2-0=101 vreg1out -vd((vrop0+25r) /sumrp vp6 mp0 2-0=110 vreg1out -vd((vrop0+29r) /sumrp vp7 vgp1 mp0 2-0=111 vreg1out -vd((vrop0+33r) /sumrp vp8 mp1 2-0=000 vreg1out -vd((vrop0+33r+vrcp0) /sumrp vp9 mp1 2-0=001 vreg1out -vd((vrop0+34r+vrcp0) /sumrp vp10 mp1 2-0=010 vreg1out -vd((vrop0+35r+vrcp0) /sumrp vp11 mp1 2-0=011 vreg1out -vd((vrop0+36r+vrcp0) /sumrp vp12 mp1 2-0=100 vreg1out -vd((vrop0+37r+vrcp0) /sumrp vp13 mp1 2-0=101 vreg1out -vd((vrop0+38r+vrcp0) /sumrp vp14 mp1 2-0=110 vreg1out -vd((vrop0+39r+vrcp0) /sumrp vp15 vgp8 mp1 2-0=111 vreg1out -vd((vrop0+40r+vrcp0) /sumrp vp16 mp2 2-0=000 vreg1out -vd((vrop0+45r+vrcp0) /sumrp vp17 mp2 2-0=001 vreg1out -vd((vrop0+46r+vrcp0) /sumrp vp18 mp2 2-0=010 vreg1out -vd((vrop0+47r+vrcp0) /sumrp vp19 mp2 2-0=011 vreg1out -vd((vrop0+48r+vrcp0) /sumrp vp20 mp2 2-0=100 vreg1out -vd((vrop0+49r+vrcp0) /sumrp vp21 mp2 2-0=101 vreg1out -vd((vrop0+50r+vrcp0) /sumrp vp22 mp2 2-0=110 vreg1out -vd((vrop0+51r+vrcp0) /sumrp vp23 vgp20 mp2 2-0=111 vreg1out -vd((vrop0+52r+vrcp0) /sumrp vp24 mp3 2-0=000 vreg1out -vd((vrop0+68r+vrcp0) /sumrp vp25 mp3 2-0=001 vreg1out -vd((vrop0+69r+vrcp0) /sumrp vp26 mp3 2-0=010 vreg1out -vd((vrop0+70r+vrcp0) /sumrp vp27 mp3 2-0=011 vreg1out -vd((vrop0+71r+vrcp0) /sumrp v2p8 mp3 2-0=100 vreg1out -vd((vrop0+72r+vrcp0) /sumrp vp29 mp3 2-0=101 vreg1out -vd((vrop0+73r+vrcp0) /sumrp vp30 mp3 2-0=110 vreg1out -vd((vrop0+74r+vrcp0) /sumrp vp31 vgp43 mp3 2-0=111 vreg1out -vd((vrop0+75r+vrcp0) /sumrp vp32 mp4 2-0=000 vreg1out -vd((vrop0+80r+vrcp0) /sumrp vp33 mp4 2-0=001 vreg1out -vd((vrop0+81r+vrcp0) /sumrp vp34 mp4 2-0=010 vreg1out -vd((vrop0+82r+vrcp0) /sumrp vp35 mp4 2-0=011 vreg1out -vd((vrop0+83r+vrcp0) /sumrp vp36 mp4 2-0=100 vreg1out -vd((vrop0+84r+vrcp0) /sumrp vp37 mp4 2-0=101 vreg1out -vd((vrop0+85r+vrcp0) /sumrp vp38 mp4 2-0=110 vreg1out -vd((vrop0+86r+vrcp0) /sumrp vp39 vgp55 mp4 2-0=111 vreg1out -vd((vrop0+87r+vrcp0) /sumrp vp40 mp5 2-0=000 vreg1out -vd((vrop0+87r+vrcp0+vrcp1) /sumrp vp41 mp5 2-0=001 vreg1out -vd((vrop0+91r+vrcp0+vrcp1) /sumrp vp42 mp5 2-0=010 vreg1out -vd((vrop0+95r+vrcp0+vrcp1) /sumrp vp43 mp5 2-0=011 vreg1out -vd((vrop0+99r+vrcp0+vrcp1) /sumrp vp44 mp5 2-0=100 vreg1out -vd((vrop0+103r+vrcp0+vrcp1) /sumrp vp45 mp5 2-0=101 vreg1out -vd((vrop0+107r+vrcp0+vrcp1) /sumrp vp46 mp5 2-0=110 vreg1out -vd((vrop0+111r+vrcp0+vrcp1) /sumrp vp47 vgp62 mp5 2-0=111 vreg1out -vd((vrop0+115r+vrcp0+vrcp1) /sumrp vp48 vgp63 - vreg1out -vd((vrop0+120r+vrcp0+vrcp1) /sumrp vp49 sumrp = 128r +vrop0+ vrop1+ vrcp0+ vrcp1; sumrn = 128r+ vron0+ vron1+ vrcn0 + vrcn1 vd=( vreg1out -vgs) [ sumrp (sumrn/ (sumrp+sumrn))]/ [sumrp sumrn/ (sumrp+sumrn) +exvr] table 5.12: voltage calculation formula (positive polarity) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.76- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 table 5.13: voltage calculation formula of grayscale voltage (positive polarity) grayscale voltage formula v0 vinp0 v1 vinp1 v2 v8+(v1-v8)*(30/48) v3 v8+(v1-v8)*(23/48) v4 v8+(v1-v8)*(16/48) v5 v8+(v1-v8)*(12/48) v6 v8+(v1-v8)*(8/48) v7 v8+(v1-v8)*(4/48) v8 vinp2 v9 v20+(v8-v20)*(22/24) v10 v20+(v8-v20)*(20/24) v11 v20+(v8-v20)*(18/24) v12 v20+(v8-v20)*(16/24) v13 v20+(v8-v20)*(14/24) v14 v20+(v8-v20)*(12/24) v15 v20+(v8-v20)*(10/24) v16 v20+(v8-v20)*(8/24) v17 v20+(v8-v20)*(6/24) v18 v20+(v8-v20)*(4/24) v19 v20+(v8-v20)*(2/24) v20 vinp3 v21 v43+(v20-v43)*(22/23) v22 v43+(v20-v43)*(21/23) v23 v43+(v20-v43)*(20/23) v24 v43+(v20-v43)*(19/23) v25 v43+(v20-v43)*(18/23) v26 v43+(v20-v43)*(17/23) v27 v43+(v20-v43)*(16/23) v28 v43+(v20-v43)*(15/23) v29 v43+(v20-v43)*(14/23) v30 v43+(v20-v43)*(13/23) v31 v43+(v20-v43)*(12/23) v32 v43+(v20-v43)*(11/23) v33 v43+(v20-v43)*(10/23) v34 v43+(v20-v43)*(9/23) v35 v43+(v20-v43)*(8/23) v36 v43+(v20-v43)*(7/23) v37 v43+(v20-v43)*(6/23) v38 v43+(v20-v43)*(5/23) v39 v43+(v20-v43)*(4/23) v40 v43+(v20-v43)*(3/23) v41 v43+(v20-v43)*(2/23) v42 v43+(v20-v43)*(1/23) v43 vinp4 v44 v55+(v43-v55)*(22/24) v45 v55+(v43-v55)*(20/24) v46 v55+(v43-v55)*(18/24) v47 v55+(v43-v55)*(16/24) v48 v55+(v43-v55)*(14/24) v49 v55+(v43-v55)*(12/24) v50 v55+(v43-v55)*(10/24) v51 v55+(v43-v55)*(8/24) v52 v55+(v43-v55)*(6/24) v53 v55+(v43-v55)*(4/24) v54 v55+(v43-v55)*(2/24) v55 vinp5 v56 v62+(v55-v62)*(44/48) v57 v62+(v55-v62)*(40/48) v58 v62+(v55-v62)*(36/48) v59 v62+(v55-v62)*(32/48) v60 v62+(v55-v62)*(25/48) v61 v62+(v55-v62)*(18/48) v62 vinp6 v63 vinp7 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.77- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 reference voltage macro adjustment value formula pin vgn0 - vreg1out -vd*vron0 /sumrn vn0 mn0 2-0=000 vreg1out -vd((vron0+5r) /sumrn vn1 mn0 2-0=001 vreg1out -vd((vron0+9r) /sumrn vn2 mn0 2-0=010 vreg1out -vd((vron0+13r) /sumrn vn3 mn0 2-0=011 vreg1out -vd((vron0+17r) /sumrn vn4 mn0 2-0=100 vreg1out -vd((vron0+21r) /sumrn vn5 mn0 2-0=101 vreg1out -vd((vron0+25r) /sumrn vn6 mn0 2-0=110 vreg1out -vd((vron0+29r) /sumrn vn7 vgn1 mn0 2-0=111 vreg1out -vd((vron0+33r) /sumrn vn8 mn1 2-0=000 vreg1out -vd((vron0+33r+vrcn0) /sumrn vn9 mn1 2-0=001 vreg1out -vd((vron0+34r+vrcn0) /sumrn vn10 mn1 2-0=010 vreg1out -vd((vron0+35r+vrcn0) /sumrn vn11 mn1 2-0=011 vreg1out -vd((vron0+36r+vrcn0) /sumrn vn12 mn1 2-0=100 vreg1out -vd((vron0+37r+vrcn0) /sumrn vn13 mn1 2-0=101 vreg1out -vd((vron0+38r+vrcn0) /sumrn vn14 mn1 2-0=110 vreg1out -vd((vron0+39r+vrcn0) /sumrn vn15 vgn8 mn1 2-0=111 vreg1out -vd((vron0+40r+vrcn0) /sumrn vn16 mn2 2-0=000 vreg1out -vd((vron0+45r+vrcn0) /sumrn vn17 mn2 2-0=001 vreg1out -vd((vron0+46r+vrcn0) /sumrn vn18 mn2 2-0=010 vreg1out -vd((vron0+47r+vrcn0) /sumrn vn19 mn2 2-0=011 vreg1out -vd((vron0+48r+vrcn0) /sumrn vn20 mn2 2-0=100 vreg1out -vd((vron0+49r+vrcn0) /sumrn vn21 mn2 2-0=101 vreg1out -vd((vron0+50r+vrcn0) /sumrn vn22 mn2 2-0=110 vreg1out -vd((vron0+51r+vrcn0) /sumrn vn23 vgn20 mn2 2-0=111 vreg1out -vd((vron0+52r+vrcn0) /sumrn vn24 mn3 2-0=000 vreg1out -vd((vron0+68r+vrcn0) /sumrn vn25 mn3 2-0=001 vreg1out -vd((vron0+69r+vrcn0) /sumrn vn26 mn3 2-0=010 vreg1out -vd((vron0+70r+vrcn0) /sumrn vn27 mn3 2-0=011 vreg1out -vd((vron0+71r+vrcn0) /sumrn vnp8 mn3 2-0=100 vreg1out -vd((vron0+72r+vrcn0) /sumrn vn29 mn3 2-0=101 vreg1out -vd((vron0+73r+vrcn0) /sumrn vn30 mn3 2-0=110 vreg1out -vd((vron0+74r+vrcn0) /sumrn vn31 vgn43 mn3 2-0=111 vreg1out -vd((vron0+75r+vrcn0) /sumrn vn32 mn4 2-0=000 vreg1out -vd((vron0+80r+vrcn0) /sumrn vn33 mn4 2-0=001 vreg1out -vd((vron0+81r+vrcn0) /sumrn vn34 mn4 2-0=010 vreg1out -vd((vron0+82r+vrcn0) /sumrn vn35 mn4 2-0=011 vreg1out -vd((vron0+83r+vrcn0) /sumrn vn36 mn4 2-0=100 vreg1out -vd((vron0+84r+vrcn0) /sumrn vn37 mn4 2-0=101 vreg1out -vd((vron0+85r+vrcn0) /sumrn vn38 mn4 2-0=110 vreg1out -vd((vron0+86r+vrcn0) /sumrn vn39 vgn55 mn4 2-0=111 vreg1out -vd((vron0+87r+vrcn0) /sumrn vn40 mn5 2-0=000 vreg1out -vd((vron0+87r+vrcn0+vrcn1) /sumrn vn41 mn5 2-0=001 vreg1out -vd((vron0+91r+vrcn0+vrcn1) /sumrn vn42 mn5 2-0=010 vreg1out -vd((vron0+95r+vrcn0+vrcn1) /sumrn vn43 mn5 2-0=011 vreg1out -vd((vron0+99r+vrcn0+vrcn1) /sumrn vn44 mn5 2-0=100 vreg1out -vd((vron0+103r+vrcn0+vrcn1)/sumrn vn45 mn5 2-0=101 vreg1out -vd((vron0+107r+vrcn0+vrcn1)/sumrn vn46 mn5 2-0=110 vreg1out -vd((vron0+111r+vrcn0+vrcn1)/sumrn vn47 vgn62 mn5 2-0=111 vreg1out -vd((vron0+115r+vrcn0+vrcn1)/sumrn vn48 vgn63 - vreg1out -vd((vron0+120r+vrcn0+vrcn1)/sumrn vn49 sumrp = 128r +vrop0+ vrop1+ vrcp0+ vrcp1; sumrn = 128r+ vron0+ vron1+ vrcn0 + vrcn1 vd = (vreg1out -vgs) [sumrp(sumrn/(sumrp+sumrn))]/[ sumrp(sumrn/(sumrp+sumrn)+exvr) table 5.14: voltage calculation formula (negative polarity) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.78- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 grayscale voltage formula v0 vinn0 v1 vinn1 v2 v8+(v1-v8)*(30/48) v3 v8+(v1-v8)*(23/48) v4 v8+(v1-v8)*(16/48) v5 v8+(v1-v8)*(12/48) v6 v8+(v1-v8)*(8/48) v7 v8+(v1-v8)*(4/48) v8 vinn2 v9 v20+(v8-v20)*(22/24) v10 v20+(v8-v20)*(20/24) v11 v20+(v8-v20)*(18/24) v12 v20+(v8-v20)*(16/24) v13 v20+(v8-v20)*(14/24) v14 v20+(v8-v20)*(12/24) v15 v20+(v8-v20)*(10/24) v16 v20+(v8-v20)*(8/24) v17 v20+(v8-v20)*(6/24) v18 v20+(v8-v20)*(4/24) v19 v20+(v8-v20)*(2/24) v20 vinn3 v21 v43+(v20-v43)*(22/23) v22 v43+(v20-v43)*(21/23) v23 v43+(v20-v43)*(20/23) v24 v43+(v20-v43)*(19/23) v25 v43+(v20-v43)*(18/23) v26 v43+(v20-v43)*(17/23) v27 v43+(v20-v43)*(16/23) v28 v43+(v20-v43)*(15/23) v29 v43+(v20-v43)*(14/23) v30 v43+(v20-v43)*(13/23) v31 v43+(v20-v43)*(12/23) v32 v43+(v20-v43)*(11/23) v33 v43+(v20-v43)*(10/23) v34 v43+(v20-v43)*(9/23) v35 v43+(v20-v43)*(8/23) v36 v43+(v20-v43)*(7/23) v37 v43+(v20-v43)*(6/23) v38 v43+(v20-v43)*(5/23) v39 v43+(v20-v43)*(4/23) v40 v43+(v20-v43)*(3/23) v41 v43+(v20-v43)*(2/23) v42 v43+(v20-v43)*(1/23) v43 vinn4 v44 v55+(v43-v55)*(22/24) v45 v55+(v43-v55)*(20/24) v46 v55+(v43-v55)*(18/24) v47 v55+(v43-v55)*(16/24) v48 v55+(v43-v55)*(14/24) v49 v55+(v43-v55)*(12/24) v50 v55+(v43-v55)*(10/24) v51 v55+(v43-v55)*(8/24) v52 v55+(v43-v55)*(6/24) v53 v55+(v43-v55)*(4/24) v54 v55+(v43-v55)*(2/24) v55 vinn5 v56 v62+(v55-v62)*(44/48) v57 v62+(v55-v62)*(40/48) v58 v62+(v55-v62)*(36/48) v59 v62+(v55-v62)*(32/48) v60 v62+(v55-v62)*(25/48) v61 v62+(v55-v62)*(18/48) v62 vinn6 v63 vinn7 table 5.15: voltage calculation formula of grayscale voltage (negative polarity) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.79- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 relationship between gram data and output level (normally white panel, gram d ata=0) figure 5.19: relationship between source output and vcom negative polarity po sitive polarity 000000 111111 ram data v63 v0 output level figure 5.20: relationship between gram data and output level (normal white panel rev =1) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.80- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.11 power on/off sequence the following are the sequences of register setting flow that applied to this driver driving the t ft display, when operate in register-content interface mode. display on/off set flow display on flow " display on" display on gon = "1" dte = "1" d1-0 = "10" display on gon = "1" dte = "1" d1-0 = "11" wait 2 frames or more display off flow display off g on = "1" dte = "1" d1-0 = "10" wait 2 frames or more display off gon = "0" d te = "0" d1-0 = "01" "display off" figure 5.21: display on/off set flow f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.81- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 sleep mode set up flow sleep in set s leep release from sleep mode slp= "0" display on flow display off flow set sleep (slp = "1") s leep mode figure 5.22: sleep mode setting flow s tandby mode set up flow standby set s tandby release from sleep mode stb= "0" display on flow display off flow set standby (stb = "1") s tandby mode figure 5.23: standby mode setting flow f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.82- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 deep standby mode set up flow wait >20ms deep s tandby set deep s tandby power supply setting display on flow display off flow set standby (stb = "1") set deep standby ( dp_stb = "1") set deep standby ( dp_stb = "0") release from deep s tandby (stb = "0") release d eep standby figure 5.24: deep standby mode setting flow f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.83- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 power on/off setting up flow set gon=1, dte=1, d [1-0]=11 display off flow display off n ormal display dte = "1", d[1-0]="11" g on = "1" display on setting bits power off flow set gon, dte, d[1-0] power on flow dte=0 d [1:0]=00 gon=0 power supply initial setting display off setting wait >5ms iovcc v ci hw reset or vci,iovcc simultaneously registers setting before p ower supply startup power supply operation setting registers setting for p ower supply startup vrh[3:0] vdv[4:0] vcm[5:0] bt[2:0] ape=1 ap[2:0]=100 wait >20ms set other register w ait >20ms set display on sequence s ap=1 display off power supply halt a pe=0 ap[2:0]=000 sap=0 iovcc v ci or vci,iovcc simultaneously power off flow figure 5.25: power supply setting flow f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.84- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.12 input / output pin state 5.12.1 output pins output or bi-directional pins after power on after hardware reset db17 to db0 (output driver) high-z (inactive) high-z (inactive) sdo high-z (inactive) high-z (inactive) te low low table 5.16: characteristics of output pins 5.12.2 input pins input pins during power on process after power on after hardware reset during power off process nreset input valid input valid input valid input valid ncs input invalid input valid input valid input invalid nwr_scl input invalid input valid input valid input invalid nrd input invalid input valid input valid input invalid dnc input invalid input valid input valid input invalid sdi input invalid input valid input valid input invalid vsync input invalid input valid input valid input invalid hsync input invalid input valid input valid input invalid de input invalid input valid input valid input invalid dotclk input invalid input valid input valid input invalid db[17:0] input invalid input valid input valid input invalid osc, im3~0 input invalid input valid input valid input invalid test2-1 input invalid input valid input valid input invalid table 5.17: characteristics of input pins f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.85- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.13 otp programing 5.13.1 otp table otp_index (hex) d7 d6 d5 d4 d3 d2 d1 d0 ref. register 00 id17_1 id16_1 id15_1 id14_1 id13_1 id12_1 id11_1 id10_1 dah 01 id27_1 id26_1 id25_1 id24_1 id23_1 id22_1 id21_1 id20_1 dbh 02 id37_1 id36_1 id35_1 id34_1 id33_1 id32_1 id31_1 id30_1 dch 03 id17_2 id16_2 id15_2 id14_2 id13_2 id12_2 id11_2 id10_2 dah 04 id27_2 id26_2 id25_2 id24_2 id23_2 id22_2 id21_2 id20_2 dbh 05 id37_2 id36_2 id35_2 id34_2 id33_2 id32_2 id31_2 id30_2 dch 06 id17_3 id16_3 id15_3 id14_3 id13_3 id12_3 id11_3 id10_3 dah 07 id27_3 id26_3 id25_3 id24_3 id23_3 id22_3 id21_3 id20_3 dbh 08 id37_3 id36_3 id35_3 id34_3 id33_3 id32_3 id31_3 id30_3 dch 09 id17_4 id16_4 id15_4 id14_4 id13_4 id12_4 id11_4 id10_4 dah 0a id27_4 id26_4 id25_4 id24_4 id23_4 id22_4 id21_4 id20_4 dbh 0b id37_4 id36_4 id35_4 id34_4 id33_4 id32_4 id31_4 id30_4 dch 0c id17_5 id16_5 id15_5 id14_5 id13_5 id12_5 id11_5 id10_5 dah 0d id27_5 id26_5 id25_5 id24_5 id23_5 id22_5 id21_5 id20_5 dbh 0e id37_5 id36_5 id35_5 id34_5 id33_5 id32_5 id31_5 id30_5 dch 0f id17_6 id16_6 id15_6 id14_6 id13_6 id12_6 id11_6 id10_6 dah 10 id27_6 id26_6 id25_6 id24_6 id23_6 id22_6 id21_6 id20_6 dbh 11 id37_6 id36_6 id35_6 id34_6 id33_6 id32_6 id31_6 id30_6 dch 12 id17_7 id16_7 id15_7 id14_7 id13_7 id12_7 id11_7 id10_7 dah 13 id27_7 id26_7 id25_7 id24_7 id23_7 id22_7 id21_7 id20_7 dbh 14 id37_7 id36_7 id35_7 id34_7 id33_7 id32_7 id31_7 id30_7 dch 15 id17_8 id16_8 id15_8 id14_8 id13_8 id12_8 id11_8 id10_8 dah 16 id27_8 id26_8 id25_8 id24_8 id23_8 id22_8 id21_8 id20_8 dbh 17 id37_8 id36_8 id35_8 id34_8 id33_8 id32_8 id31_8 id30_8 dch 18 valid_id1_8 valid_id1_7 valid_id1_6 valid_id1_5 valid_id1_4 valid_id1_3 valid_id1_2 valid_id1_1 --- 19 valid_id2_8 valid_id2_7 valid_id2_6 valid_id2_5 valid_id2_4 valid_id2_3 valid_id2_2 valid_id2_1 -- 1a valid_id3_8 valid_id3_7 valid_id3_6 valid_id3_5 valid_id3_4 valid_id3_3 valid_id3_2 valid_id3_1 -- 1b valid_vcm_1 vcm5_1 vcm4_1 vcm3_1 vcm2_1 vcm1_1 vcm0_1 29h 1c valid_vdv_1 vdv4_1 vdv3_1 vdv2_1 vdv1_1 vdv0_1 13h 1d valid_vcm_2 vcm5_2 vcm4_2 vcm3_2 vcm2_2 vcm1_2 vcm0_2 29h 1e valid_vdv_2 vdv4_2 vdv3_2 vdv2_2 vdv1_2 vdv0_2 13h 1f valid_vcm_3 vcm5_3 vcm4_3 vcm3_3 vcm2_3 vcm1_3 vcm0_3 29h 20 valid_vdv_3 vdv4_3 vdv3_3 vdv2_3 vdv1_3 vdv0_3 13h 21 valid_vcm_4 vcm5_4 vcm4_4 vcm3_4 vcm2_4 vcm1_4 vcm0_4 29h 22 valid_vdv_4 vdv4_4 vdv3_4 vdv2_4 vdv1_4 vdv0_4 13h 23 valid_vcm_5 vcm5_5 vcm4_5 vcm3_5 vcm2_5 vcm1_5 vcm0_5 29h 24 valid_vdv_5 vdv4_5 vdv3_5 vdv2_5 vdv1_5 vdv0_5 13h 25 valid_vcm_6 vcm5_6 vcm4_6 vcm3_6 vcm2_6 vcm1_6 vcm0_6 29h 26 valid_vdv_6 vdv4_6 vdv3_6 vdv2_6 vdv1_6 vdv0_6 13h 27 valid_vcm_7 vcm5_7 vcm4_7 vcm3_7 vcm2_7 vcm1_7 vcm0_7 29h 28 valid_vdv_7 vdv4_7 vdv3_7 vdv2_7 vdv1_7 vdv0_7 13h 29 valid_vcm_8 vcm5_8 vcm4_8 vcm3_8 vcm2_8 vcm1_8 vcm0_8 29h 2a valid_vdv_8 vdv4_8 vdv3_8 vdv2_8 vdv1_8 vdv0_8 13h 2b valid_panel ddvdh_tri sm_panel ss_panel gs_panel rev_panel bgr_panel 98h f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.86- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.13.2 otp programming flow normal on write otp data to re late register set bt=0x01 (r 10h=0x1190h) otp_key (r a5h=0xaa55) set vpp_sel=1' (r a4h=0x0002) set vpp_en=1 (r a4h=0x0042h) set otp index/mask (r a3h=0x????h) set otp start o tp_prog=1' (ra4h=0x0043h) re-power on wait 1ms w ait 1us wait 10ms set otp end o tp_prog=0' (ra4h=0x0042h) wait 1ms wait 100us w ait 1ms (ra4h=0x0040h) set vpp_sel=0' (r a4h=0x0000) set vpp_en=0 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.87- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.13.3 otp sequence step operation 1 power on and ic normal operation 2 write optimized value to related register command register description id1 rdah set id1 lcd version id2 id3 power control 4 power control 7 rdbh rdch r13h r29h set id2 lcd version set id3 lcd version set vdv[4:0] vcom amplitude set vcm[5:0] vcomh voltage 3 set bt[2:0]=0x01 (r10h=0x1190) 4 set otp_key (ra5h=0xaa55) 5 set otp_sel (ra4h=0x0002) 6 set otp_en (ra4h=0x0042) 7 set otp index index description 00h,01h,02h id1~id3 index 1bh,1ch vdv,vcm vcom valid 2bh panel characteristic, valid_panel 8 set otp_mask=0x00h, programming the entire bit of one parameter. 9 set otp start otp_prog=1 (ra4h=0x0043h) 10 wait 10ms 11 set otp start otp_prog=0 (ra4h=0x0042h) complete programming one parameter to otp. if continue to programming other parameter, return to step (4). otherwise power off module, and re-power on again. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.88- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.13.4 otp read flow otp read flow set otp index (ra3h=0x??00h) end set otp_por=0 ( ra4h=0x0000) read another otp index yes n o keep the otp_index set otp_por=1 (rf3h=0x0200) read the command ra4h and g et the otp_data f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.89- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 5.14 content adaptive brightness control (cabc) function the HX8347-B has support content adaptive brightness control (cabc) function and will o utput one pwm signal to external led driver ic. the pwm signal is automatics adjust output duty by display image for saving led backlight power consumption. example: image a: -20% brightness reduction image b: -30% brightness reduction image c: -10% brightness reduction transition t ime 50% 0% 100% time 80% 70% 90% transition t ime transition t ime image a: b rightness reduction ratio 20% image b: b rightness reduction ratio 30% image c: b rightness reduction ratio 10% figure 5.26: example of cabc function the general block diagram of the cabc and the brightness control is illustrated below: /0"7 @cb + + , # ,i !,0 /0 ) @ ,"hp$pb /i ,<&=(> @ ,"hp(pb + ! !, !,,i !,,i !,,i !,,i ,*"hn(n=)cc ,*"hn$n=) <$=(>hn((n=)cc <$=(>hn($ndn$(ndn$$n=) 2d .2d !,"d "7@ *, b figure 5.27: cabc block diagram f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.90- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 module architectures t he HX8347-B can support two module architectures for cabc operation. the bl bit setting of r3dh can be used to select used display module architecture. white led driver circuit for display backlight is located on the main pwb, not in the display module both in architecture i and ii. architecture i cabc_ pwm_out 1. bl =`1` of rb3h 2. led backlight brightness for the display is control led by external output ? cabc_pwm_out ? . architecture ii 1. bl =`0` of rb3h 2. led backlight brightness data for the display is read with dbv[7:0] bits of r3ch. 3. read commands rb2h should be synchronized with v-sync. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.91- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 brightness control block t here is an external output signal from brightness block, cabc_pwm_out, to control the led driver ic in order to control display brightness. there are resister bits, dbv[7:0] of rb1h, for display brightness of manual brightness setting. the cabc_pwm_out duty is calculated as dbv[7:0]/255 x cabc duty (generated after one-frame display data content analysis). for example: cabc_pwm_out period = 2.95 ms, and dbv[7:0](rb2h) = 228 dec and c abc duty is 74%. then cabc_pwm_out duty = 228 / 255 x 74% o 65.90%. correspond to the cabc_pwm_out period = 2.95 ms, the high-level of cabc_pwm_out (high effective) = 1.94ms, and the low-level of cabc_pwm_out = 1.01ms. on off cabc_ pwm_out duty = 100% maximum duty = 33% duty = 65.90% duty = 100% off one period display brightness / figure 5.28: cabc_pwm_out output duty when architecture ii module is used ( b l =0) with the example below, the cabc_pwm_out is always output low and the dbv[7:0](rb2h) will be read a value as 169 dec (169/255 o 6 6.27%). f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.92- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 minimum brightness setting of cabc function c abc function is automatically reduced backlight brightness based on image contents. in the case of the combination with the cabc or manual brightness setting, display brightness is too dark. it must affect image quality degradation. cabc minimum brightness setting ( cmb[7:0] bits of rbeh) works to avoid too much brightness reduction. when cabc is active, cabc can not reduce the display brightness to less than cabc minimum brightness setting. image processing function works as normal, even if the brightness can not be changed. this function does not affect the other function, manual brightness setting. manual brightness can be set the display brightness to less than cabc minimum brightness. smooth transition and dimming function can work as normal. when display brightness is turned off ( bctrl=0 of rb3h), cabc minimum brightness setting is ignored. read cabc minimum brightness cmb[7:0] (rbfh) always reads the setting value. display dimming a dimming function (how fast to change the brightness from old to new level and what are brightness levels during the change) is used when changing from one brightness level to another to avoid flicker in the actual display module. this dimming function curve is the same in increment and decrement directions. figure 5.29: dimming function luminance luminance dimming hysteresis step up time time without dimming with dimming f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.93- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6. command d0 d1 d2 d3 d4 d5 d6 d7 im3~im0 = w 0000 w 8080 mcu 16bits parallel interface type i d0 d1 d2 d3 d4 d5 d6 d7 im3~im0 = w 0001 w 8080 mcu 8bits parallel interface type i db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 d0 d1 d2 d3 d4 d5 d6 d7 im3~im0 = w 1000 w 8080 mcu 18bits parallel interface type i im3~im0 = w 1001 w 8080 mcu 9bits parallel interface type i register co n tent d8 d9 d10 d11 d12 d13 d14 d15 register co ntent d8 d9 d10 d11 d12 d13 d14 d15 1st transfer 2 nd transfer d8 d9 d10 d11 d12 d13 d14 d15 register co ntent d0 d1 d2 d3 d4 d5 d6 d7 register co ntent d8 d9 d10 d11 d12 d13 d14 d15 1 st transfer 2n d transfer db1 db2 db3 db4 db5 db6 db7 db8 db10 db11 db12 db13 db14 db15 db16 db17 d0 d1 d2 d3 d4 d5 d6 d7 im3~im0 = w 0010 w 8080 mcu 16bits parallel interface type ii db10 db11 db12 db13 db14 db15 db16 db17 d0 d1 d2 d3 d4 d5 d6 d7 im3~im0 = w 0011 w 8080 mcu 8bits parallel interface type ii db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 d0 d1 d2 d3 d4 d5 d6 d7 im3~im0 = w 1010 w 8080 mcu 18bits parallel interface type ii db9 db10 db11 db12 db13 db14 db15 db16 db17 im3~im0 = w 1011 w 8080 mcu 9bits parallel interface type ii register con tent d8 d9 d10 d11 d12 d13 d14 d15 db10 db11 db12 db13 db14 db15 db16 db17 r egister con tent d8 d9 d10 d11 d12 d13 d14 d15 1st transfer 2 nd transfer d8 d9 d10 d11 d12 d13 d14 d15 register co ntent db9 db10 db11 db12 db13 db14 db15 db16 db17 d0 d1 d2 d3 d4 d5 d6 d7 register co ntent d8 d9 d10 d11 d12 d13 d14 d15 1 st transfer 2 n d transfer db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 db8 db8 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.94- himax confidential this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. december, 2009 HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.1 command set upper code lower code register r/w rs rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 ir index w 0 * * * * * * * * * id6 id5 id4 id3 id2 id1 id0 r00h driver id code r 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 r01h driver output control rw 1 0 0 0 0 0 sm (0) 0 ss (0) 0 0 0 0 0 0 0 0 r02h lcd driving control rw 1 0 0 0 0 0 0 b/c (0) 0 0 0 0 0 0 0 0 0 r03h entry mode rw 1 tri (0) dfm (0) 0 bgr (0) 0 0 0 0 0 0 i/d1 (1) i/d0 (1) am (0) 0 0 0 r05h 16 bits data mapping rw 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 epf[1:0] (00) r07h display control 1 rw 1 0 0 ptde[1:0] (00) 0 0 0 basee (0) 0 0 gon (0) dte (0) cl (0) 0 d1 (0) d0 (0) r08h display control 2 rw 1 0 0 0 0 fp[3:0] (1000) 0 0 0 0 bp[3:0] (1000) r09h display control 3 rw 1 0 0 0 0 0 0 pts[1:0] (00) 0 0 ptg[1:0] (00) isc[3:0] (0000) r0ah display control 4 rw 1 0 0 0 0 0 0 0 0 te_mo de(0) 0 0 0 teoe (0) tei[2:0] (000) r0ch rgb interface control 1 rw 1 0 ecn[2:0] (000) 0 0 0 rm (0) 0 0 dm[1:0] (00) 0 0 rim[1:0] (00) r0dh te output position rw 1 0 0 0 0 0 0 0 tep[8:0] (0 0000 0000) r0fh rgb interface control 2 rw 1 0 0 0 0 0 0 0 0 0 0 0 vspl (0) hspl (0) 0 epl (0) dpl (0) r10h power control 1 rw 1 0 0 0 sap0 (0) 0 bt2 (1) bt1 (1) bt0 (0) ape (0) ap2 (0) ap1 (0) ap0 (0) 0 0 slp (0) stb (0) r11h power control 2 rw 1 0 0 0 0 0 dc12 (1) dc11 (1) dc10 (1) 0 dc02 (1) dc01 (1) dc00 (1) 0 0 0 0 r12h power control 3 rw 1 0 0 0 0 0 0 ddvd h_tri( 0) xdk (0) vcire (0) 0 0 vrh3 (0) vrh2 (0) vrh1 (0) vrh0 (0) r13h power control 4 rw 1 0 0 0 vdv4 (0) vdv3 (0) vdv2 (0) vdv1 (0) vdv0 (0) 0 0 0 0 0 0 0 0 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.95- himax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 upper code lower code register r/w rs rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 r20h ram address set rw 1 0 0 0 0 0 0 0 0 ad7 (0) ad6 (0) ad5 (0) ad4 (0) ad3 (0) ad2 (0) ad1 (0) ad0 (0) r21h ram address set rw 1 0 0 0 0 0 0 0 ad16 (0) ad15 (0) ad14 (0) ad13 (0) ad12 (0) ad11 (0) ad10 (0) ad9 (0) ad8 (0) r22h ram data write/read rw 1 ram wd17-0 /ram (rd17-0) r29h power control 7 rw 1 0 0 0 0 0 0 0 0 0 0 vcm[5:0] (0 0000) r2bh frame rate control rw 1 0 0 0 0 0 0 0 0 0 0 0 0 frs[3:0] (1101) r30h r control (1) rw 1 0 0 0 0 0 mp12 (0) mp11 (0) mp10 (0) 0 0 0 0 0 mp02 (0) mp01 (0) mp00 (0) r31h r control (2) rw 1 0 0 0 0 0 mp32 (0) mp31 (0) mp30 (0) 0 0 0 0 0 mp22 (0) mp21 (0) mp20 (0) r32h r control (3) rw 1 0 0 0 0 0 mp52 (0) mp 51 (0) mp 50 (0) 0 0 0 0 0 mp42 (0) mp41 (0) mp40 (0) r35h r control (4) rw 1 0 0 0 0 0 cp12 (0) cp11 (0) cp10 (0) 0 0 0 0 0 cp 02 (0) cp 01 (0) cp00 (0) r36h r control (5) rw 1 0 0 0 op14 (0) op13 (0) op12 (0) op11 (0) op10 (0) 0 0 0 0 op03 (0) op02 (0) op01 (0) op00 (0) r37h r control (6) rw 1 0 0 0 0 0 mn12 (0) mn11 (0) mn10 (0) 0 0 0 0 0 mn02 (0) mn01 (0) mn00 (0) r38h r control (7) rw 1 0 0 0 0 0 mn32 (0) mn31 (0) mn30 (0) 0 0 0 0 0 mn22 (0) mn21 (0) mn20 (0) r39h r control (8) rw 1 0 0 0 0 0 mn52 (0) mn51 (0) mn50 (0) 0 0 0 0 0 mn42 (0) mn41 (0) mn40 (0) r3ch r control (9) rw 1 0 0 0 0 0 cn12 (0) cn11 (0) cn10 (0) 0 0 0 0 0 cn02 (0) cn01 (0) cn00 (0) r3dh r control (10) rw 1 0 0 0 on14 (0) on13 (0) on12 (0) on11 (0) on10 (0) 0 0 0 0 on03 (0) on02 (0) on01 (0) on00 (0) r50h horizontal start rw 1 0 0 0 0 0 0 0 hsa[7:0] (0x00) r51h horizontal end rw 1 0 0 0 0 0 0 0 hse[7:0] (0xef) r52h vertical start rw 1 0 0 0 0 0 0 0 vsa[7:0] (0x00) r53h vertical end rw 1 0 0 0 0 0 0 0 vse[7:0] (0x13f) r60h gate scan start position rw 1 gs (0) 0 nl[5:0] (1 0111) 0 0 0 0 0 scn4 (0) scn3 (0) scn2 (0) scn1 (0) scn0 (0) r61h base image control rw 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ndl(0) vle(0) rev(0) r66h spi read/write control w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.96- himax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 upper code lower code register r/w rs rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 r6ah vertical scroll control rw 1 0 0 0 0 0 0 0 vl8(0) vl7(0) vl6(0) vl5(0) vl4(0) vl3(0) vl2(0) vl1(0) vl0(0) r80h partial image 1 display position rw 1 0 0 0 0 0 0 0 ptdp 08 ptdp0 7 ptdp0 6 ptdp0 5 ptdp0 4 ptdp0 3 ptdp0 2 ptdp0 1 ptdp0 0 r81h partial image 1 area (start line) rw 1 0 0 0 0 0 0 0 ptsa0 8 ptsa0 7 ptsa0 6 ptsa0 5 ptsa04 ptsa03 ptsa02 ptsa01 ptsa00 r82h partial image 1 area (end line) rw 1 0 0 0 0 0 0 0 ptea0 8 ptea0 7 ptea0 6 ptea0 5 ptea04 ptea03 ptea02 ptea01 ptea00 r83h partial image 2 display position rw 1 0 0 0 0 0 0 0 ptdp 18 ptdp1 7 ptdp1 6 ptdp1 5 ptdp1 4 ptdp1 3 ptdp1 2 ptdp1 1 ptdp1 0 r84h partial image 2 area (start line) rw 1 0 0 0 0 0 0 0 ptsa1 8 ptsa1 7 ptsa1 6 ptsa1 5 ptsa14 ptsa13 ptsa12 ptsa11 ptsa10 r85h partial image 2 area (end line) rw 1 0 0 0 0 0 0 0 ptea1 8 ptea1 7 ptea1 6 ptea1 5 ptea14 ptea13 ptea12 ptea11 ptea10 r90h panel interface control 1 rw 1 0 0 0 0 0 0 divi1(0) divi00 (0) 0 0 0 rtni4 (1) rtni3 (0) rtni2 (0) rtni1 (0) rtni0 (0) r92h panel interface control 2 rw 1 0 0 0 0 0 nowi 2(1) nowi1(1) nowi 0(0) 0 0 0 0 0 0 0 0 r97h panel interface control 3 rw 0 0 0 0 now e3 now e2 nowe1 nowe 0 0 0 0 0 0 0 0 0 r98h panel interface control 4 rw 0 0 0 0 0 0 0 0 0 0 0 sm_pa nel ss_pan el gs_pa nel rev_p anel bgr_p anel ra2h otp vcm status and enable rw 1 0 0 vcm_ d5 vcm_ d4 vcm_ d3 vcm_ d2 vcm_d1 vcm_ d0 0 0 0 0 0 0 0 vcm_e n ra3h otp data and index rw 1 otp_in dex7 otp_in dex6 otp_in dex5 otp_in dex4 otp_i ndex3 otp_i ndex2 otp_inde x1 otp_i ndex0 otp_m ask7 otp_m ask6 otp_m ask5 otp_m ask4 otp_m ask3 otp_m ask2 otp_m ask1 otp_m ask0 ra4h otp function rw 1 0 0 0 0 0 0 0 0 load_d isable vpp_e n otp_p or otp_p we otp_p tm1 otp_p tm0 vpp_s el otp_p rog ra5h otp programming id key rw 1 key15 key14 key13 key12 key1 1 key1 0 key9 key8 key7 key6 key5 key4 key3 key2 key1 key0 rb1h write display brightness w 1 dbv7 dbv6 dbv5 dbv4 dbv3 dbv2 dbv1 dbv0 rb2h read display brightness r 1 dbv7 dbv6 dbv5 dbv4 dbv3 dbv2 dbv1 dbv0 rb3h write ctrl display value w 1 x x bctrl x dd bl x x rb4h read ctrl display value r 1 x x bctrl x dd bl x x f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.97- himax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 upper code lower code register r/w rs rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 rb5h write content adaptive brightness control value w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c[1:0] rb6h read content adaptive brightness control value r 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c[1:0] rbeh write cabc minimum brightness w 1 0 0 0 0 0 0 0 0 cmb[7:0] rbfh read caba minimum brightness r 1 0 0 0 0 0 0 0 0 cmb[7:0] rc7h cabc control 1 w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ledon pol pwmp ol rc8h cabc control 2 w 1 0 0 0 0 0 0 0 0 pwm_period[7:0] rdah id1 rw 1 0 0 0 0 0 0 0 0 id1[7:0] rdbh id2 rw 1 0 0 0 0 0 0 0 0 id2[7:0] rdch id3 rw 1 0 0 0 0 0 0 0 0 id3[7:0] re6h deep stand by mode control w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dstb rf3h otp data read r 1 0 0 0 0 0 0 0 0 otp_data_read[7:0] rf4h id otp cnt r 1 0 0 id1_cnt[3:0] 0 id2_cnt[3:0] 0 id3_cnt[3:0] rf5h vcom otp cnt r 1 0 0 0 0 0 0 0 vcm_cnt[3:0] 0 vdv_cnt[3:0] f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.98- h imax confidential this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. december, 2009 HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.2 index register rb15 * * * * id6 id5 id4 id3 id2 id1 id0 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 w 0 r/w rs * * * * * figure 6.1: index register i ndex register (ir) specifies index of the register from r00h to rffh. it sets the register number (id6-0) in the range from 000000b to 1111111b in binary form. 6.3 driver id code(r00h) rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 r 0 r/w rs l7 l6 l5 l4 l3 l2 l1 l0 0 0 0 0 0 0 0 0 the device id 9325h is read out when read this register. 6.4 driver output control (r01h) figure 6.2: driver output control register (r01h) ss: t he source driver output shift direction selected. the shift direction from s1 to s528 when ss = 0. and shift direction from s528 to s1 when ss = 1. and if the bgr = 0, -p.99- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 g320 g 319 g2 g1 HX8347-B tft panel g1, g2, g3, g4,.... g317, g318, g319, g320 g318 g4 g317 g3 g2 to g320 g1 to g319 0 0 sm gs scan direction 0 1 1 0 1 1 o dd- number line even- number line g320 g 319 g2 g1 HX8347-B tft panel g320, g319, g318, g317,.... g4, g3, g2, g1 g318 g4 g317 g3 g2 to g320 g1 to g319 odd- number line even- number line g320 g 319 g2 g1 HX8347-B tft panel g320, g318, g316, g314,.... g6, g4, g2 g2 to g320 g1 to g319 odd- number line even- number line g320 g 319 g2 g1 HX8347-B tft panel g1, g3, g5,.... g315, g317, g319, g320 g2 to g320 g1 to g319 odd- number line even- number line g2, g4, g6,.... g 314, g316, g318, g320 g319, g317, g315, g313,.... g 5, g3, g1 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.100- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.5 driving control (r02h) figure 6.3: driving control register (r02h) b/c: s pecify lcd driving inversion type 0 frame inversion 1 line inversion 6.6 entry mode (r03h) rb15 tri dfm 0 bgr 0 0 0 0 org 0 i/d1 i/d0 am rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 w 1 r/w rs f igure 6.4: entry control register (r03h) am: t he updating direction as write data to gram. the data will be written vertically when am=1; the data will be written horizontally when am=0. in case of window address range is given, data will be written to the gram in the range of the window address according to am & i/d [1..0]. i/d[1..0]: the ac will incremented by 1 after data written to gram if i/d = 1; the ac will decremented by 1 after data written to gram if i/d=0. the following figure depicts the update method with i/d1-0 & am bit. i /d[1:0]= 00 hortizontal:decrement vertical:decrement i/d[1:0]= 01 hortizontal:increment vertical:decrement i/d[1:0]= 10 hortizontal:decrement vertical:increment i/d[1:0]= 11 hortizontal:increment vertical:increment am=0 horizontal b e b e b e b e am=1 vertical b e b e b e b e figure 6.5: address direction settings org: m oves the origin address according to the id setting when a window address area is made. this function is enabled when writing data with the window address area using high-speed ram write. org = 0 : the origin address is not moved. in this case, specify the address to start write operation according to the gram address map within the window address area. org = 1: the original address 00000h moves according to the i/d[1:0] setting. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.101- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 bgr: r gb direction selection for color filter setting. bgr = 0 : s1,s2,s3 filter order=r,g,b bgr = 1 : s1,s2,s3 filter order=b,g,r tri: w hen tri=1, a pixel data is written to gram through transfer 3 times 8-bit bus interface. dfm: specify the data format when tri=1. 01 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b 5 b 4 b 3 b 2 b 1 b 0 1 1 1st transfer 2nd transfer r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 0 0 16bit interface ram write data transfer d fmtri 1st transfer 2nd transfer 8 0system 16bit interface msb mode (2 transfers/pixel) 262,144 colors available 80system 16bit interface (1 transfer/pixel) 65536 colors available gram d ata rgb a ssignment gram d ata rgb a ssignment db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b 5 b 4 b 3 b 2 b 1 b 0 1st transfer 2nd transfer 8 0system 16bit interface lsb mode (2 transfers/pixel) 262,144 colors available gram d ata rgb a ssignment db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 17 db 16 db 2 db 1 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 figure 6.6: the setting of dfm and tri (80-system 16-bit interface) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.102- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 1 1 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 1st transfer 2nd transfer 3rd transfer r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 0 0 8 bit interface ram write data transfer dfmtri 1st transfer 2nd transfer 8 0system 8bit interface (3 transfers/pixel) 262,144 color s available 80system 8bit interface (2 transfers/pixel) 65,536 colors available gram d ata rgb a ssignment gram d ata rgb a ssignment db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 1 0 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 1st transfer 2nd transfer 3rd transfer 8 0system 8bit interface (3 transfers/pixel) 262,144 colors available gram d ata rgb a ssignment db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 figure 6.7: the setting of dfm and tri (80-system 8-bit interface) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.103- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.7 16 bits data mapping (r05h) figure 6.8: 16 bits color data mapping register 2 (r05h) e pf[1:0]: 65k color mode data format 1 0 db 1 7 0 0 1 6 bits color mapping epf0 epf1 data bus rgb a ssignment 0 1 r5 r4 r3 r2 r1 0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 0 data r ead db 1 6 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 10 db 11 db 12 db 13 db 14 db 15 db 1 db 1 7 db 1 6 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 10 db 11 db 12 db 13 db 14 db 15 db 1 db 1 7 data bus rgb a ssignment r5 r4 r3 r2 r1 1 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 1 data r ead db 1 6 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 10 db 11 db 12 db 13 db 14 db 15 db 1 db 1 7 db 1 6 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 10 db 11 db 12 db 13 db 14 db 15 db 1 db 1 7 data bus rgb a ssignment r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 data r ead db 1 6 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 10 db 11 db 12 db 13 db 14 db 15 db 1 db 1 7 db 1 6 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 10 db 11 db 12 db 13 db 14 db 15 db 1 db 1 7 data bus rgb a ssignment r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 data r ead db 1 6 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 10 db 11 db 12 db 13 db 14 db 15 db 1 db 1 7 db 1 6 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 10 db 11 db 12 db 13 db 14 db 15 db 1 1 1 green d ata=even red d ata=blue data yes b ypass no yes g 0 copy to r0/b0 no f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.104- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.8 display control 1 (r07h) figure 6.9: display control register 1 (r07h) d 1C0: when d1 = 1, display is on; when d1 = 0, display is off. when display is off, the display data is retained in the gram, and can be instantly displayed by setting d1 = 1. when d1= 0, the display is off with the entire source outputs are set to the vssd level. because of this, the HX8347-B can control the charging current for the lcd with ac driving. control the display on/off while control gon and dte. when d1C0 = 01, the internal display of the HX8347-B is performed although the actual display is off. when d1-0 = 00, the internal display operation halts and the display is off. d1 d0 basee source output HX8347-B internal display operations gate-driver control signals 0 0 x vssd halt halt 0 1 x vssd operate operate 1 0 x =pts(0,0) operate operate 1 1 0 =pts(0,0) operate operate 1 1 1 base image display operate operate note: data can be written to the gram from the mpu regardless of the content of d1-0. cl: cl = 1, the display mode is set to the 8-color display mode. cl number of display colors 0 262,144 1 8 dte, gon: s pecify the output level of gate line. gon dte gate output 0 x vgh 1 0 vgl 1 1 vgh/vgl note: gon bit is used in the gate driver. control according to the bits values is executed by the gate driver. basee: b ase image display enable bit. when basee = 0, no base image is displayed. the HX8347-B drives liquid crystal at non-lit display level or displays only partial images. when basee = 1, the base image is displayed. the d[1:0] setting has higher priority over the basee setting. partial image 2 and partial image 1 enable bits ptde1/0 = 0: turns off partial image. only base image is displayed. ptde1/0 = 1: turns on partial image. set the base image display enable bit to 0 (basee = 0). f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.105- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.9 display control 2 (r08h) rb15 0 0 0 0 fp3 fp2 fp1 fp0 0 0 0 0 bp3 bp2 bp1 bp0 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 w 1 r/w rs figure 6.10: display control register 2 (r08h) b p3-0: specify the amount of scan line for back porch (bp). fp3-0: specify the amount of scan line for front porch (fp). the setting vale, ensure that: bp + fp Q QQ Q 16 lines pb R RR R 2 lines fp R RR R 2 lines in external display interface mode, the bp start on the falling edge of vsync signal, followed by he display operation. the fp starts after driving the number of scan line set with nl4-0. after the fp, the blank period continues until the next input of the vsync signal. fp3 fp2 fp1 fp0 bp3 bp2 bp1 bp0 number of fp line number of bp line 0 0 0 0 ignore 0 0 0 1 ignore 0 0 1 0 2 lines 0 0 1 1 3 lines : : : : : 1 1 0 1 13 lines 1 1 1 0 14 lines 1 1 1 1 ignore table 6.1: bp/fp bits setting vsync display area bp fp f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.106- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.10 display control 3 (r09h) figure 6.11: display control register 3 (r09h) p tg1-0: specify the scan mode of gate driver in non-display area. ptg1 ptg0 gate outputs in non-display area 0 0 normal drive 0 1 --- 1 0 interval scan 1 1 --- isc3-0: specify the scan cycle of gate driver when ptg1-0=10 in non-display area. then scan cycle is set to an odd number from 0~31.the polarity is inverted every scan cycle. isc3 isc2 isc1 isc0 scan cycle f flm = 60hz 0 0 0 0 0 frame - 0 0 0 1 1 frame - 0 0 1 0 3 frames 50 ms 0 0 1 1 5 frames 84 ms 0 1 0 0 7 frames 117 ms 0 1 0 1 9 frames 150 ms 0 1 1 0 11 frames 184 ms 0 1 1 1 13 frames 217 ms 1 0 0 0 15 frames 251 ms 1 0 0 1 17 frames 284 ms 1 0 1 0 19 frames 317 ms 1 0 1 1 21 frames 351 ms 1 1 0 0 23 frames 384 ms 1 1 0 1 25 frames 418 ms 1 1 1 0 27 frames 451 ms 1 1 1 1 29 frames 484 ms f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.107- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 pts[1:0]: s pecify the scan mode of source in non-display area (front/back porch period and blank area between partial displays). pts[1:0] source/vcom outputs in non-display area refresh cycle white 00 non-refresh cycle source=v63 vcom=vcoml refresh cycle black 01 non-refresh cycle source=v0 vcom=vcoml refresh cycle white 10 non-refresh cycle source=gnd vcom=gnd refresh cycle white 11 non-refresh cycle source=hi-z vcom=hi-z 6.11 display control 4 (r0ah) figure 6.12: display control register 4 (r0bh) tei[2:0]: set the output interval of fmark signal according to the display data rewrite cycle and data transfer rate. tei[2:0] output interval 000 1 frame 001 2 frame 010 3 frame 011 4 frame 100 5 frame 101 6 frame 110 7 frame 111 8 frame teoe: when teoe=1, HX8347-B starts to output te signal. temode: specify the tearing-effect mode. when temode = 0: the tearing effect output line (te) consists of back porch information only. w hen temode =1: the tearing effect output line (te) consists of both back porch and h-blanking information note: d uring stand by mode with tearing effect line on, tearing effect output pin active low f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.108- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.12 rgb interface control 1 (r0ch) figure 6.13: rgb interface control register (r0ch) r im1-0: specify the transfer mode of rgb interface. rim, dm, rm must be set before lcd display operation through the rgb interface. during the lcd display, not allow changing the setting vale. rim1 rim0 transfer mode 0 0 18-bit bus rgb interface mode (1 transfer/pixel) 0 1 16-bit bus rgb interface mode (1 transfer/pixel) 1 0 6-bit bus rgb interface mode (3 transfers/pixel) 1 1 ignore dm1-0: s pecify the operation mode of lcd display. dm1-0 allows the switch operation between the internal clock operation mode and external display interface mode (rgb and vsync interface mode), but cant switch between rgb and vsync interface mode. dm1 dm0 operation mode 0 0 system interface 0 1 rgb interface 1 0 vsync interface 1 1 ignore rm: specify the access interface of gram. the setting value is not affected by the operation mode of lcd display. for example: in rgb interface operation mode, the data can be access to gram through rgb interface when rm=1, and then also access to gram through system interface when rm=0. rm access interface 0 system interface vsync interface 1 rgb interface note: (1) the register is set only through the system interface. (2) a dotclk input and data transfers must be executed in dot unit (r, g, b) for 6-bit bus rgb interface mode. enc[2:0]: set the gram write cycle through the rgb interface enc[2:0] gram write cycle 000 1 frame 001 2 frame 010 3 frame 011 4 frame 100 5 frames 101 6 frames 110 7 frames 111 8 frame f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.109- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.13 te output position (r0dh) figure 6.14: te output position (r0dh) tep[8:0] sets the output position of frame cycle (te signal). w hen tep[8:0]=0, a high-active pulse te is output at the start of back porch period for one display line period (1h).make sure the 9h000 Q tep Q bp+nl+fp tep[8:0] te output position 9h000 0 th line 9h001 1 st line 9h002 3 rd line 9h003 4 th line : : : : 9h175 373 rd line 9h176 374 th line 9h177 375 th line 6.14 rgb interface control 2 (r0fh) figure 6.15: rgb interface control register 2 (r0fh) epl: s pecify the polarity of enable pin in rgb interface mode. epl enable pin gram address write to gram operation 0 low update enable write data to db17-0 0 high keep disable disable 1 low keep disable disable 1 high update enable write data to db17-0 vspl: the polarity of vsync pin. when vspl=0, the vsync pin is low active. when vspl=1, the vsync pin is high active. hspl: the polarity of hsync pin. when hspl=0, the hsync pin is low active. when hspl=1, the hsync pin is high active. dpl: the polarity of dotclk pin. when dpl=0, the data is read on the rising edge of dotclk signal. when dpl=1, the data is read on the falling edge of dotclk signal. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.110- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.15 power control 1 (r10h ) figure 6.16: power control register 1 (r10h) stb: w hen stb = 1, the HX8347-B into the standby mode, where all display operation stops, suspend all the internal operations including the internal r-c oscillator thus the current consumption can be reduced. slp: when slp = 1, the HX8347-B into the sleep mode, where the internal display operations are suspend except for the r-c oscillator, thus the current consumption can be reduced. ap2C0: adjust the amount of fixed current from the fixed current source for the operational amplifier in the power supply circuit. when the amount of fixed current is increased, the lcd driving capacity and the display quality are high, but the current consumption is increased. this is a tradeoff, adjust the fixed current by considering both the display quality and the current consumption. during no display operation, when ap[2:0] = 000, the current consumption can be reduced by stopping the operations of operational amplifier and step-up circuit. ap2 ap1 ap0 gamma driver amplifiers source driver amplifiers 0 0 0 stop stop 0 0 1 1.00 1.00 0 1 0 1.00 0.75 0 1 1 1.00 0.50 1 0 0 0.75 1.00 1 0 1 0.75 0.75 1 1 0 0.75 0.50 1 1 1 0.5 0.50 bt2C0: s witch the output factor for step-up circuit. the lcd drive voltage level can be selected according to the characteristic of liquid crystal which panel used. lower amplification of the step-up circuit consumes less current and then the power consumption can be reduced. bt2 bt1 bt0 ddvdh vcl vgh vgl 0 0 0 5.0v -vci 3ddvdh -vci-2ddvdh 0 0 1 5.0v -vci 3ddvdh -2ddvdh 0 1 0 5.0v -vci 3ddvdh vci-2ddvdh 0 1 1 5.0v -vci vci+2ddvdh -vci-2ddvdh 1 0 0 5.0v -vci vci+2ddvdh -2ddvdh 1 0 1 5.0v -vci vci+2ddvdh vci-2ddvdh 1 1 0 5.0v -vci 2ddvdh -2ddvdh 1 1 1 5.0v -vci 2ddvdh -vci-ddvdh note: when vci = 2.8v, ddvdh_tri=0 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.111- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 bt2 bt1 bt0 ddvdh vcl vgh vgl 0 0 0 6.1v -vci setting inhabited setting inhabited 0 0 1 6.1v -vci 3ddvdh -2ddvdh 0 1 0 6.1v -vci 3ddvdh vci-2ddvdh 0 1 1 6.1v -vci vci+2ddvdh -vci-2ddvdh 1 0 0 6.1v -vci vci+2ddvdh -2ddvdh 1 0 1 6.1v -vci vci+2ddvdh vci-2ddvdh 1 1 0 6.1v -vci 2ddvdh -2ddvdh 1 1 1 6.1v -vci 2ddvdh -vci-ddvdh note: when vci = 2.8v, ddvdh_tri=1 sap: source driver output control s ap=0, source driver is disabled. sap=1, source driver is enabled. when starting the charge-pump of lcd in the power on stage, make sure that sap=0, and set the sap=1, after starting up the lcd power supply circuit. ape: power supply enable bit. se t ape = 1 to start the generation of power supply according to the power supply startup sequence. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.112- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.16 power control 2 (r11h) figure 6.17: power control register 2 (r11h) dc0[2:0]: s et the operating frequency for the step-up circuit 1. when using the higher frequency, the driving ability of the step-up circuit and the display quality are high, but the current consumption is increased. the tradeoff is between the display quality and the current consumption. dc02 dc01 dc00 operation frequency of step-up circuit 1 and extra step-up circuit 1 0 0 0 ? x h line frequency 0 0 1 ? x h line frequency 0 1 0 1 x h line frequency 0 1 1 1.5 x h line frequency 1 0 0 2 x h line frequency 1 0 1 3 x h line frequency 1 1 0 4 x h line frequency 1 1 1 8 x h line frequency dc1[2:0]: set the operating frequency for the step-up circuit 2. when using the higher frequency, the driving ability of the step-up circuit and the display quality are high, but the current consumption is increased. the tradeoff is between the display quality and the current consumption. dc12 dc11 dc10 operation frequency of step-up circuit 2 and extra step-up circuit 2 0 0 0 ? x h line frequency 0 0 1 ? x h line frequency 0 1 0 1 x h line frequency 0 1 1 1.5 x h line frequency 1 0 0 2 x h line frequency 1 0 1 3 x h line frequency 1 1 0 4 x h line frequency 1 1 1 8 x h line frequency note : ensure that the operation frequency of step-up circuit 1 R step-up circuit 2 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.113- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.17 power control 3 (r12h) figure 6.18: power control register 3 (r12h) vrh[3:0]: s et the magnification of amplification for vreg1out voltage. (vcom, reference voltage for grayscale voltage). xdk, ddvdh_tri: s pecify the ratio of step-up circuit for ddvdh voltage generation. ddvdh_tri xdk step-up circuit 1 capacitor connection pins used 0 0 2 x vci c11p, c11n 0 1 2 x vci c11p, c11n, c12p, c12n 1 0 3 x vci c11p, c11n, c12p, c12n 1 1 setting inhabited setting inhabited vcire: select the external reference voltage vci or internal reference voltage vcir. vcire=0, external reference voltage vci (default) vcire =1, internal reference voltage 2.5v vcire=0 vcire=1 vrh3 vrh2 vrh1 vrh0 vreg1out vrh3 vrh2 vrh1 vrh0 vreg1out 0 0 0 0 halt 0 0 0 0 halt 0 0 0 1 vcix2.00 0 0 0 1 2.5vx2.00=5.000v 0 0 1 0 vcix2.05 0 0 1 0 2.5vx2.05=5.125v 0 0 1 1 vcix2.10 0 0 1 1 2.5vx2.10=5.250v 0 1 0 0 vcix2.20 0 1 0 0 2.5vx2.20=5.500v 0 1 0 1 vcix2.30 0 1 0 1 2.5vx2.30=5.750v 0 1 1 0 vcix2.40 0 1 1 0 2.5vx2.40=6.000v 0 1 1 1 vcix2.40 0 1 1 1 2.5vx2.40=6.000v 1 0 0 0 vcix1.60 1 0 0 0 2.5vx1.60=4.000v 1 0 0 1 vcix1.65 1 0 0 1 2.5vx1.65=4.125v 1 0 1 0 vcix1.70 1 0 1 0 2.5vx1.70=4.250v 1 0 1 1 vcix1.75 1 0 1 1 2.5vx1.75=4.375v 1 1 0 0 vcix1.80 1 1 0 0 2.5vx1.80=4.500v 1 1 0 1 vcix1.85 1 1 0 1 2.5vx1.85=4.625v 1 1 1 0 vcix1.90 1 1 1 0 2.5vx1.90=4.75v 1 1 1 1 vcix1.95 1 1 1 1 2.5vx1.95=4.875v f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.114- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.18 power control 4 (r13h) figure 6.19: power control register 4 (r13h) vdv4-0: s ets the amplification factors for vcom. vdv4 vdv3 vdv2 vdv1 vdv0 vcom amplitude vdv4 vdv3 vdv2 vdv1 vdv0 vcom amplitude 0 0 0 0 0 vrge1out x 0.70 0 0 0 0 0 vrge1out x 0.94 0 0 0 0 1 vrge1out x 0.72 0 0 0 0 1 vrge1out x 0.96 0 0 0 1 0 vrge1out x 0.74 0 0 0 1 0 vrge1out x 0.98 0 0 0 1 1 vrge1out x 0.76 0 0 0 1 1 vrge1out x 1.00 0 0 1 0 0 vrge1out x 0.78 0 0 1 0 0 vrge1out x1.02 0 0 1 0 1 vrge1out x 0.80 0 0 1 0 1 vrge1out x 1.04 0 0 1 1 0 vrge1out x 0.82 0 0 1 1 0 vrge1out x1.06 0 0 1 1 1 vrge1out x 0.84 0 0 1 1 1 vrge1out x 1.08 0 1 0 0 0 vrge1out x 0.86 0 1 0 0 0 vrge1out x1.10 0 1 0 0 1 vrge1out x 0.88 0 1 0 0 1 vrge1out x 1.12 0 1 0 1 0 vrge1out x 0.90 0 1 0 1 0 vrge1out x1.14 0 1 0 1 1 vrge1out x 0.92 0 1 0 1 1 vrge1out x 1.16 0 1 1 0 0 vrge1out x 0.94 0 1 1 0 0 vrge1out x1.18 0 1 1 0 1 vrge1out x 0.96 0 1 1 0 1 vrge1out x 1.20 0 1 1 1 0 vrge1out x 0.98 0 1 1 1 0 vrge1out x1.22 0 1 1 1 1 vrge1out x 1.00 0 1 1 1 1 vrge1out x 1.24 note: set the vcom amplitude is lower than 6.0v. 6.19 ram address set (r20h~r21h) figure 6.20: ram address register (r20h) figure 6.21: ram address register (r21h) ad[16:0]: s et gram addresses to the address counter (ac) before access the gram. once the gram data is written, the ac is automatically updated according to the am and i/d bits. during the standby mode, the gram cannot be accessed. ad[16:0] gram setting 00000h C 000efh bitmap data for g1 00100h C 001efh bitmap data for g2 00200h C 002efh bitmap data for g3 : : 13d00h C 13defh bitmap data for g318 13d00h C 13eefh bitmap data for g319 13f00h C 13fefh bitmap data for g320 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.115- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.20 ram data write/read (r22h) figure 6.22: read data register (r22h) w d[17:0]: transforms the data into 18-bit bus before written to gram through the write data register (wdr). after a write operation is issued, the address is automatically updated according to the am and i/d bits. rd[17:0]: read 18-bit data from gram through the read data register (rdr). when the data is read by microcomputer, the first-word read immediately after the gram address setting is latched from the gram to the internal read-data latch. the data on the data bus (d17C0) becomes invalid and the second-word read is normal. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.116- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 gram data & r gb mapping read data register 16-bit bus interface output 9-bit bus interface o utput 8-bit bus interface / serial data transfer interface output r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 gram data & r gb mapping gram data & rgb mapping read data register read data register 1st transfer (upper) 2ndtransfer (lower) 2ndtransfer (lower) 1st transfer (upper) r 5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 rd 17 rd 16 rd 15 rd 14 rd 13 rd 12 rd 11 rd 10 rd 9 rd 8 rd 7 rd 6 rd 5 rd 4 rd 3 rd 2 rd 1 rd 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 rd 17 rd 16 rd 15 rd 14 rd 13 rd 12 rd 11 rd 10 rd 9 rd 8 rd 7 rd 6 rd 5 rd 4 rd 3 rd 2 rd 1 rd 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 rd 17 rd 16 rd 15 rd 14 rd 13 rd 12 rd 11 rd 10 rd 9 rd 8 rd 7 rd 6 rd 5 rd 4 rd 3 rd 2 rd 1 rd 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 gram data & r gb mapping read data register 18-bit bus interface output r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 db 1 7 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 rd 17 rd 16 rd 15 rd 14 rd 13 rd 12 rd 11 rd 10 rd 9 rd 8 rd 7 rd 6 rd 5 rd 4 rd 3 rd 2 rd 1 rd 0 figure 6.23: output data read from gram through read data register in 18-/16- /9- /8-bit interface mode f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.117- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.21 power control 7 (r29h ) figure 6.24: power control register 7 (r29h) v cm[5:0]: sets the vcom high voltage. vcm[5:0] vcom high voltage vcm[5:0] vcom high voltage 6'h00 vrge1out x 0.685 6'h20 vrge1out x 0.845 6'h01 vrge1out x 0.690 6'h21 vrge1out x 0.850 6'h02 vrge1out x 0.695 6'h22 vrge1out x 0.855 6'h03 vrge1out x 0.700 6'h23 vrge1out x 0.860 6'h04 vrge1out x 0.705 6'h24 vrge1out x 0.865 6'h05 vrge1out x 0.710 6'h25 vrge1out x 0.870 6'h06 vrge1out x 0.715 6'h26 vrge1out x 0.875 6'h07 vrge1out x 0.720 6'h27 vrge1out x 0.880 6'h08 vrge1out x 0.725 6'h28 vrge1out x 0.885 6'h09 vrge1out x 0.730 6'h29 vrge1out x 0.890 6'h0a vrge1out x 0.735 6'h2a vrge1out x 0.895 6'h0b vrge1out x 0.740 6'h2b vrge1out x 0.900 6'h0c vrge1out x 0.745 6'h2c vrge1out x 0.905 6'h0d vrge1out x 0.750 6'h2d vrge1out x 0.910 6'h0e vrge1out x 0.755 6'h2e vrge1out x 0.915 6'h0f vrge1out x 0.760 6'h2f vrge1out x 0.920 6'h10 vrge1out x 0.765 6'h30 vrge1out x 0.925 6'h11 vrge1out x 0.770 6'h31 vrge1out x 0.930 6'h12 vrge1out x 0.775 6'h32 vrge1out x 0.935 6'h13 vrge1out x 0.780 6'h33 vrge1out x 0.940 6'h14 vrge1out x 0.785 6'h34 vrge1out x 0.945 6'h15 vrge1out x 0.790 6'h35 vrge1out x 0.950 6'h16 vrge1out x 0.795 6'h36 vrge1out x 0.955 6'h17 vrge1out x 0.800 6'h37 vrge1out x 0.960 6'h18 vrge1out x 0.805 6'h38 vrge1out x 0.965 6'h19 vrge1out x 0.810 6'h39 vrge1out x 0.970 6'h1a vrge1out x 0.815 6'h3a vrge1out x 0.975 6'h1b vrge1out x 0.820 6'h3b vrge1out x 0.980 6'h1c vrge1out x 0.825 6'h3c vrge1out x 0.985 6'h1d vrge1out x 0.830 6'h3d vrge1out x 0.990 6'h1e vrge1out x 0.835 6'h3e vrge1out x 0.995 6'h1f vrge1out x 0.840 6'h3f vrge1out x 1.000 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.118- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.22 frame rate control (r2bh) figure 6.25: frame rate register 7 (r2bh) f rs[3:0]: set the frame rate when using the internal oscillator. frs[3:0] frame rate(hz) frs[3:0] frame rate(hz) 4'h0 30 4'h8 50 4'h1 35 4'h9 55 4'h2 40 4'ha 60 4'h3 45 4'hb 70 4'h4 65 4'hc 80 4'h5 75 4'hd 90 4'h6 120 4'he 100 4'h7 130 4'hf 110 6.23 gamma control register (r30h~r3dh) figure 6.26: gamma control register 1~10 (r30h~r3dh) mp5-0 [2:0]: gamma adjustment registers for positive polarity output cp1-0 [2:0]: gamma gradient adjustment registers for positive polarity output mn5-0 [2:0]: gamma adjustment registers for negative polarity output cn1-0 [2:0]: gamma gradient adjustment registers for negative polarity output op0 [3:0]/op1 [4:0]: amplification adjustment resistor for positive polarity output on0 [3:0]/on1 [4:0]: amplification average adjustment resistor for negative polarity output for details, refer to gamma adjustment function section. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.119- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.24 get scan lines (r45h) figure 6.27: get sacn lines register (r45h) HX8347-B can return the current scanline n; customer can use to update the display. the f irst scanline is defined as the first line as line 0. 6.25 horizontal start (r50h) figure 6.28: horizontal ram start address position register (r50h) 6.26 horizontal end (r51h ) figure 6.29: horizontal ram end address position register (r51h) 6.27 vertical start (r52h) figure 6.30: vertical ram start address position register (r52h) 6.28 vertical end (r53h) figure 6.31: vertical ram end address position register (r53h) has[7:0]/hea[7:0]: s pecify the horizontal start/end positions of a window for access in gram. data can be written to the gram from the address specified by has[7:0] to the address specified by hea[7:0].ensure that 00h has[7:0] hea[7:0] efh f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.120- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 vsa[8:0]/vea[8:0]: s pecify the vertical start/end positions of a window for access in gram. data can be written to the gram from the address specified by vsa[8:0] to the address specified by vea[8:0]. ensure that 000h vsa[8:0] vea[8:0] 13fh window address 0000h 13fefh h sa hea gram address space vsa v ea window address setting range 00h has[7:0] hea[7:0] efh 000h vsa[8:0] vea[8:0] 13fh note: t he window address range must be within the gram address space. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.121- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.29 gate scan start position (r60h) figure 6.32: gate scan position register (r60h) s cn[5:0]: set the scanning starting position of the gate driver. scanning start position sm=0 sm=1 scn[5:0] gs=0 gs=1 gs=0 gs=1 00h g1 g320 g1 g320 01h g9 g312 g17 g304 02h g17 g304 g33 g288 03h g25 g296 g49 g272 04h g33 g288 g65 g256 05h g41 g280 g81 g240 06h g49 g272 g97 g224 07h g57 g264 g113 g208 08h g65 g256 g129 g192 09h g73 g248 g145 g176 0ah g81 g240 g161 g160 0bh g89 g232 g177 g144 0ch g97 g224 g193 g128 0dh g105 g216 g209 g112 0eh g113 g208 g2 g96 0fh g121 g200 g18 g80 10h g129 g192 g34 g64 11h g137 g184 g50 g48 12h g145 g176 g66 g32 13h g153 g168 g82 g16 14h g161 g160 g98 g319 15h g169 g152 g114 g303 16h g177 g144 g130 g287 17h g185 g136 g146 g271 18h g193 g128 g162 g255 19h g201 g120 g178 g239 1ah g209 g112 g194 g223 1bh g217 g104 g114 g207 1ch g225 g96 g130 g191 1dh g233 g88 g146 g175 1eh g241 g80 g162 g159 1fh g249 g72 g178 g143 20h g257 g64 g194 g127 21h g265 g56 g210 g111 22h g273 g48 g226 g95 23h g281 g40 g242 g79 24h g289 g32 g258 g63 25h g297 g24 g274 g47 26h g305 g16 g290 g31 27h g313 g8 g306 g15 28h~3fh setting disabled f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.122- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 note: (1) dont set nl, scn over the end position of gate line (g220) (2) set nl4-0 and scn4-0 so that the number for the end position of the gate line scan will not exceed 220. figure 6.33: scn bits and scanning start position for gate driver nl[4:0]: s pecify the number of scan lines for the lcd driver can be adjusted by every 8 lines. select the setting value for the panel size or higher. nl[5:0] lcd drive line nl[5:0] lcd drive line 00h 8 line 14h 168 line 01h 16 line 15h 176 line 02h 24 line 16h 184 line 03h 32 line 17h 192 line 04h 40 line 18h 200 line 05h 48 line 19h 208 line 06h 56 line 1ah 216 line 07h 64 line 1bh 224 line 08h 72 line 1ch 232 line 09h 80 line 1dh 240 line 0ah 88 line 1eh 248 line 0bh 96 line 1fh 256 line 0ch 104 line 20h 264 line 0dh 112 line 21h 272 line 0eh 120 line 22h 280 line 0fh 128 line 23h 288 line 10h 136 line 24h 296 line 11h 144 line 25h 304 line 12h 152 line 26h 312 line 13h 160 line 27h 320 line others setting disabled gs: s pecify the shift direction of gate driver output. when gs = 0, the shift direction from g1 to g320. when gs = 1, the shift direction from g320 to g1. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.123- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.30 base image control (r61h) figure 6.34: base image control register (r61h) rev: r ev = 1 selects the inversion of the display of all characters and graphics. this bit allows the display of the same data on both normally-white and normally-black panels. display area rev gram data positive polarity negative polarity 0 18h00000 . . 18h3ffff v63 . . v0 v0 . . v63 1 18h00000 . . 18h3ffff v0 . . v63 v63 . . v0 vle: this bit turns on scroll mode by setting vle = 1. the scroll mode window is described by the vertical scroll area command vl[8:0] . to leave scroll mode to normal mode, th e vle bit should be set to 0. ndl: sets the source driver output level in the non-display area. non-display area ndl positive polarity negative polarity 0 v63 v0 1 v0 v63 6.31 spi read/write control (r66h) figure 6.35: spi read/write control (r66h) this register is used to control the read/write function of registers when the 8/9-bit serial i nterface is used. if users need to read back the register data by the 8/9-bit serial interface, the r/wx bit must be set as 1. rw description 0 register write mode (default) 1 register read mode f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.124- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.32 vertical scroll control (r6ah) figure 6.36: vertical scroll control (r6ah) vl[8:0]: s pecify the amount of scrolling line from 0 to 320 in the display to enable smooth vertical scrolling. vl8 vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 scrolling length 0 0 0 0 0 0 0 0 0 0 line 0 0 0 0 0 0 0 0 1 1 line 0 0 0 0 0 0 0 1 0 2 lines 0 0 0 0 0 0 0 1 1 3 lines : : : : : : : : 1 0 0 1 1 1 1 0 0 317 lines 1 0 0 1 1 1 1 1 0 318 lines 1 0 0 1 1 1 1 1 1 319 lines 6.33 partial image 1 display position (r80h) figure 6.37: partial image 1 display position (r80h) ptdp0[8:0]: s ets the display start position of partial image 1. the display areas of the partial images 1 and 2 must not overlap each another. 6.34 partial image 1 area (start line) (r81h) figure 6.38: partial image 1 area (start line) (r81h) 6.35 partial image 1 area (end line) (r82h) figure 6.39: partial image 1 area (start line) (r81h) ptsa0[8:0] ptea0[8:0]: s ets the start line address and the end line address of the ram area storing the data of partial image 1. make sure ptsa0[8:0] ptea0[8:0]. 6.36 partial image 2 display position (r83h) figure 6.40: partial image 2 display position (r83h) ptdp1[8:0]: s ets the display start position of partial image 2. the display areas of the partial images 1 and 2 must not overlap each another. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.125- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.37 partial image 2 area (start line) (r84h) figure 6.41: partial image 2 area (start line) (r84h) 6.38 partial image 2 area (end line) (r85h) figure 6.42: partial image 2 area (start line) (r85h) ptsa1[8:0] ptea1[8:0]: s ets the start line address and the end line address of the ram area storing the data of partial image 2. make sure ptsa1[8:0] ptea1[8:0]. the following example shows the setting for partial display function. base image setting basee 0 nl[5:0] 6h27 partial display 1 setting ptsa0[8:0] 9h000 ptea0[8:0] 9h00f ptdp0[8:0] 9h080 partial display 2 setting ptsa1[8:0] 9h020 ptea1[8:0] 9h02f ptdp1[8:0] 9h0c0 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.126- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.127- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.39 panel interface control 1 (r90h) figure 6.43: panel interface control 1 (r90h) rtni[4:0]: s ets 1h (line) clock number of internal clock operating mode. in this mode, HX8347-B display operation is synchronized with internal clock signal. clock cycles=1/internal operation clock frequency (fosc) rtni[4:0] clock number per line rtni[3:0] clock number per line 5b00000 127 5b10000 143 5b00001 128 5b10001 144 5b00010 129 5b10010 145 5b00011 130 5b10011 146 5b00100 131 5b10100 147 5b00101 132 5b10101 148 5b00110 133 5b10110 149 5b00111 134 5b10111 150 5b01000 135 5b11000 151 5b01001 136 5b11001 152 5b01010 137 5b11010 153 5b01011 138 5b11011 154 5b01100 139 5b11100 155 5b01101 140 5b11101 156 5b01110 141 5b11110 157 5b01111 142 5b11111 158 divi[1:0]: s pecify the division ratio of internal clocks for internal operation. when used internal clock for the display operation. divi1 divi0 division ratio internal display operation clock frequency 0 0 1 fosc / 1 0 1 2 fosc / 2 1 0 4 fosc / 4 1 1 8 fosc / 8 note: fosc = r-c oscillation frequency 6.40 panel interface control 2 (r92h) figure 6.44: panel interface control 2 (r92h) n owi[2:0]: sets the gate output non-overlap period when HX8347-B display operation is synchronized with internal clock signal. nowi[2:0] gate non-overlap period 000 invalid 001 1 clocks 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 invalid f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.128- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.41 panel interface control 3 (r97h) figure 6.45: panel interface control 5 (r97h) nowe[2:0]: sets the gate output non-overlap period when HX8347-B display operation is synchronized with rgb interface signal. nowe[3:0] gate non-overlap period nowe[3:0] gate non-overlap period 0000 setting disabled 1 000 8 clocks 0001 1 clocks 1001 9 clocks 0010 2 clocks 1010 10 clocks 0011 3 clocks 1011 11 clocks 0100 4 clocks 1100 12 clocks 0101 5 clocks 1101 setting disabled 0110 6 clocks 1110 setting disabled 0111 7 clocks 1111 setting disabled 6.42 panel interface control 4 (r98h) figure 6.46: panel interface control 4 (r98h) this command is internal use for display panel setting. r ev_p: the source output data polarity selected. when rev_p=0, the data will not reverse. when rev_p = 1, the data will reverse. bgr_p: the color filter order direction selected. when bgr_panel=0, dont reverse the bgr setting. when bgr_p = 1, the color filter order will be reversed. gs_p: the gate driver output shift direction selected. when gs_p=0, the shift direction dont reverse gs setting. when gs_p = 1, the shift direction will be reversed. ss_p: the source driver output shift direction selected. when ss_p=0, the shift direction dont reverse ss setting. when ss_p = 1, the shift direction will be reversed. sm_p: the gate scan direction selected. when sm_p=0, the shift direction dont reverse sm setting. when sm_p = 1, the shift direction will be reversed. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.129- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.43 otp vcm status and enable (ra2h) figure 6.47: otp vcm status and enable (ra2h) pgm_cnt[1:0]: otp programmed record, when vcm programming time <4. these bits are read only. otp_pgm_cnt[1:0] description 00 otp clean 01 otp programmed 1 time 10 otp programmed 2 times 11 otp programmed 3 times vcm_d[5:0]: otp vcm data read value. vcm_en: otp vcm data enable. 1: set this bit to enable otp vcm data to replace r29h vcm value. 0: default value, use r29h vcm value 6.44 otp index and otp mask (ra3h) figure 6.48: otp index and mask (ra3h) otp_index[7:0]: s et index location in otp to be programmed. otp_mask[7:0]: otp bit programming mask, if set to 1, it means the related bit in otp can not be programmed. 6.45 otp programming function (ra4h) figure 6.49: otp programming id key (ra4h) otp_prog: w hen this bit is set to 1, lsi writes data to otp from internal register. otp_ptm[1:0]: internal use, not open. otp_pwe: internal use, not open. otp_por: when set to 1, otp data can be read the related otp index data at otp_data[7:0] vpp_sel: when set to 1, internal power voltage is fed to otp. vpp_en: when set to 1, otp power op is ready. otp_load_disable : internal use, not open. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.130- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.46 otp programming id key (ra5h) figure 6.50: otp programming id key (ra5h) key[15:0]: otp programming id key protection. before writing otp programming data ra1h, it must write ra5h with 0xaa55 value first to make otp programming successfully. if ra5h is not written with 0xaa55, otp programming will be fail. see otp programming flow. . 6.47 write display brightness (rb1h) figure 6.51: write display brightness (rb1h) 6.48 read display brightness (rb2h) figure 6.52: read display brightness (rb2h) 6.49 write ctrl display value (rb3h) figure 6.53: write ctrl display value (rb3h) 6.50 read ctrl display value (rb4h) figure 6.54: read ctrl display value (rb3h) 6.51 write content adaptive brightness control value (rb5h) figure 6.55: write content adaptive brightness control value (rb5h) 6.52 read content adaptive brightness control value (rb6h) figure 6.56: read content adaptive brightness control value (rb6h) 6.53 write cabc minimum brightness (rbeh) figure 6.57: write cabc minimum brightness (rbeh) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.131- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.54 read cabc minimum brightness (rbfh) figure 6.58: read cabc minimum brightness (rbfh) these commands are used to set cabc parameter d bv[7:0]: the backlight pwm pulse output duty is equal to dbv[7:0]/255 x cabc_duty. bctrl: backlight control block on/off, this bit is always used to switch brightness for display. 0 = off (equal to dbv[7:0] = 00h) 1 = on (brightness registers are active.) dd: display dimming (only for manual brightness setting) 0 : display dimming is off. 1 : display dimming is on. bl: backlight control on/off 0 = off (completely turn off backlight circuit. control lines must be low. ) 1 = on dimming function is adapted to the brightness registers for display when bit bctrl is changed at dd=1, e.g. bctrl: 0 -> 1 or 1-> 0. when bl bit change from on to off, backlight is turned off without gradual dimming, even if dimming-on ( dd=1 ) are selected. c[1:0]: this command is used to set parameters for image content based adaptive brightness control functionality. there is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below. c1 c0 function note 0 0 off - 0 1 user interface image - 1 0 still picture - 1 1 moving image - cmb[7:0]: this command is used to set the minimum brightness value of the display for cabc function. in principle relationship is that 00h value means the lowest brightness for cabc and ffh value means the highest brightness for cabc. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.132- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.55 cabc control 1 (rc7h) figure 6.59: cabc control 1 (rc7h) ledpwmpol: t he bit is used to define polarity of ledpwm signal. bl ledpwmpol ledpwm pin 0 0 0 1 0 pwm signal 0 1 1 1 1 inversed pwm signal ledonpol: t his bit is used to control ledon pin. 0: ledon pin=l 1: ledon pin=h 6 .56 cabc control 2 (rc8h) figure 6.60: cabc control 2 (rbfh) pwm_period[7:0] : the backlight pwm output period setting. backlight pwm output period = (pwm_clk / (255x(pwm_period[7:0]+1)) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.133- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.57 id control (rdah~dch) figure 6.61: id1 (rdah) figure 6.62: id2 (rdbh) figure 6.63: id3 (rdch) i d1~id3: id setting related register. 6.58 deep stand by control (re6h) figure 6.64: deep stand by control (re6h) dp_stb: i t can let the driver into the deep standby mode. and when into deep standby, all display operation stops, including the internal r-c oscillator. in the deep standby mode, the gram data and register content are not retained. for details, please refer to 6.7 power on/off sequence section for detail use. 6 .59 otp data (rf3h) figure 6.65: otp data (rf3h) otp_data[7:0]: r ead otp data. 6.60 otp id cnt (rf4h) figure 6.66: otp id cnt (rf4h) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.134- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 6.61 otp vcom cnt (rf5h) figure 6.67: otp vcom cnt (rf3h) id3_cnt[3:0]: id3 o tp programming time counter. id2_cnt[3:0]: id2 otp programming time counter. id1_cnt[3:0]: id1 otp programming time counter. vdv_cnt[3:0]: vdv voltage otp programming time counter. vcm_cnt[3:0]: vcomh otp programming time counter. cnt[3:0] description 0000 otp clean 0001 otp programmed 1 time 0010 otp programmed 2 times 0011 otp programmed 3 times 0100 otp programmed 4 times 0101 otp programmed 5 times 0110 otp programmed 6 times 0111 otp programmed 7 times 1000 otp programmed 8 times f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.135- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 7. layout recommendation figure 7.1: layout recommendation of HX8347-B f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.136- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 7.1 maximum layout resistance name type maximum series resistance unit iovcc power supply 10 vci power supply 10 vssa power supply 10 vssd power supply 10 osc input 100 im[3:0] input 100 nrd, nwr_scl, dnc, ncs, sda input 100 nreset input 100 te, ledpwm,ledon output 100 db[17:0], i/o 100 dotclk, de, vsync, hsync input 100 vgh capacitor connection 10 vgl capacitor connection 10 vcl capacitor connection 10 ddvdh capacitor connection 10 vddd capacitor connection 10 vreg1out capacitor connection 50 c11p, c11n, c12p, c12n capacitor connection 10 c31p, c12n capacitor connection 10 c21p, c21n capacitor connection 15 c22p, c22n capacitor connection 15 testo15~0 input 100 vcomhdum, vcomldum,dummy dummy 100 vtest test pin 100 f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.137- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 7.2 external components connection capacitor recommended voltage capacity c1 (c11p/n) 6v 1f (b characteristics) c2 (c12p/n) 6v 1f (b characteristics) c3 (ddvdh) 10v 1f (b characteristics) c4 (c21p/n) 10v 1f (b characteristics) c5 (c22p/n) 10v 1f (b characteristics) c6 (vgh) 25v 1f (b characteristics) c7 (vgl) 16v 1f (b characteristics) c8 (c31p/n) 6v 1f (b characteristics) c9 (vcl) 6v 1f (b characteristics) c10(vddd) 6v 1f (b characteristics) f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.138- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 8. electrical characteristic 8.1 absolute maximum ratings item symbol unit value note power supply voltage 1 iovcc~vssd v -0.3 to +4.6 note (1),(2) power supply voltage 2 vci ~ vssa v -0.3 to +4.6 note (3) power supply voltage 3 ddvdh ~ vssa v -0.3 to +6.6 note (4) power supply voltage 4 vssa ~ vcl v -0.3 to +4.6 note (5) power supply voltage 5 ddvdh ~ vcl v -0.3 to +9 note (6) power supply voltage 6 vgh ~ vssa v -0.3 to +18.5 note (7) power supply voltage 7 vssa ~ vgl v 0 to -16.5 note (8) logic input voltage v in v -0.3 to iovcc+0.5 - logic output voltage vo v -0.3 to iovcc+0.5 - operating temperature topr -40 to +85 note (9),(10) storage temperature tstg -55 to +110 note (9),(10) note: (1) iovcc, vssd must be maintained. (2) to make sure iovcc vssd. (3) to make sure vci vssa. (4) to make sure ddvdh vssa. (5) to make sure vssa vcl. (6) to make sure ddvdh vcl. (7) to make sure vgh vssa. (8) to make sure vssa vgl vgh +|vgl| < 32v (9) for die and wafer products, specified up to +85 . (10) this temperature specifications apply to the tcp package. table 8.1: absolute maximum ratings 8 .2 esd protection level mode test condition protection level unit human body model c=100 pf, r=1.5 k d 2.0k v machine model c=200 pf, r=0.0 d 200 v table 8.2: esd protection level f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.139- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 8.3 dc characteristics spec. parameter symbol conditions min. typ. max. unit power & operating voltages io operating voltage iovcc i/o supply voltage 1.65 1.8 3.3 driver operating voltage vci operation voltage 2.3 2.8 3.3 vreg1 triple pump 3.3 4.65 5.8 source drive voltage vreg1 dual pump 3.3 4.65 4.8 ivgh=30ua (typ:bt=001) vci=2.8 dual pump tbd tbd - gate drive high voltage vgh ivgh=30ua ( typ:bt=001) vci=2.8 triple pump tbd tbd - ivgl=30ua (typ:bt=001) vci=2.8 dual pump tbd tbd - gate drive low voltage vgl ivgl=30ua ( typ:bt=001) vci=2.8 triple pump tbd tbd - drive supply voltage |vgh-vgl| - - - 30 v input / output high level input voltage vih 0.7iovcc - iovcc low level input voltage vil iovcc=1.65~1.95 vssd - 0.3iovcc high level input voltage vih 0.8iovcc - iovcc low level input voltage vil iovcc=1.95~3.3 vssd - 0.2iovcc high level output voltage voh ioh = -1.0ma 0.8iovcc - iovcc low level output voltage vol iol = +1.0ma vssd - 0.2iovcc v input leakage current iil - -1 - 1 a oscillator frequency fosc frame rate at 6 0hz,default vs and hs setting t a =25 2.76 2.85 2.94 mhz booster(vci=2.8v) dual pump iddvdh=300ua 4.8 5.0 5.2 ddvdh boost voltage1 ddvdh triple pump i ddvdh=300ua 5.9 6.1 6.3 vcl boost voltage vcl icl=-100ua -2.5 -2.65 2.75 v vcom generator(vci=2.8v) no load, dual pump 2.5 4.4 7.3 v vcom amplitude vcom no load t riple pump 2.5 4.4 8.3 v no load dual pump 2.5 3.205 4.8 v vcom high level vcomh no load t riple pump 2.5 3.205 5.8 v vcom low level vcoml no load -2.5 -1.195 vssd v source driver(typ:t a =25 vci=2.8v) vssd+1.0 ~ vreg1-1.0 - 3 d 10 d 20 mv output voltage deviation (mean value) dvos vssd+0.1v ~ v ssd+1.0 vreg1-1.0 ~ vreg1-0.1v - d 30 d 50 mv output voltage range vos - 0.1 - ddvdh-0.1 v output offset voltage voff - d 30 d 50 mv f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.140- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 current consumption(typ: t a =25 iovcc=vci=2.8v) iiovcc - tbd - ma normal operation ivci gram data = 0000h frame rate=60hz - tbd - ma iiovcc - - - 20 a sleep in ivci - - - 10 a note: vreg1/vcomh/vcoml conditions: when internal voltage vref=4.8v for dual pump and vref=5.8v for triple pump fpc m easurement point lcd panel measurement point connector pin or flex side f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.141- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 8.4 ac characteristics 8.4.1 parallel interface characteristics (8080-series mpu) figure 8.1: parallel interface characteristics (8080-series mpu) (vssa=0v, iovcc=1.65v to 3.3v, vci=2.3v to 3.3v,ta = -30 to 70 c) signal symbol parameter min. max. unit description dnc_scl t ast t aht address setup time ad dress hold time (write/read) 10 10 - - ns - ncs t chw t cs t rcs t rcsfm t csf t csh chip select h pulse width c hip select setup time (write) chip select setup time (read id) chip select setup time (read fm) chip select wait time (write/read) chip select hold time 0 15 45 355 10 10 - - - - - - ns - nwr_scl t wc twc t wrh t wrl write cycle(18bits interface) w rite cycle(8/9/16 bits 262k interface) control pulse h duration control pulse l duration 100 66 15 15 - - - ns - nrd(id) t rc t rdh t rdl read cycle (id) c ontrol pulse h duration (id) control pulse l duration (id) 160 90 45 - - - ns when read id data nrd(fm) t rcfm t rdhfm t rdlfm read cycle (fm) c ontrol pulse h duration (fm) control pulse l duration (fm) 450 90 355 - - - ns when read from frame m emory db17 to db0 t dst t dht t rat t ratfm t odh data setup time d ata hold time read access time (id) read access time (fm) output disable time 10 10 - - 20 - - 60 340 80 ns for maximum c l =30pf f or minimum c l =8pf note: the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. logic high and low levels are specified as 30% and 70% of iovcc for input signals. tf t f tr tr f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.142- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 figure 8.2: chip select timing figure 8.3: write to read and read to write timing f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.143- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 8.4.2 serial interface characteristics figure 8.4: serial interface characteristics (vssa=0v, iovcc=1.65v to 3.3v, vci=2.3v to 3.3v,ta = -30 to 70 c) parameter symbol conditions min. typ. max. unit serial clock cycle (write) scl h pulse width (write) scl l pulse width (write) t scycw t shw t slw scl 66 1 5 15 - - - - - - ns data setup time (write) data hold time (write) t sds t sdh sdi 10 1 0 - - - - ns serial clock cycle (read) scl h pulse width (read) scl l pulse width (read) t scycr t shr t slr scl 150 6 0 60 - - - - - - ns access time t acc sdi for maximum c l =30pf f or minimum c l =8pf 10 - 50 ns output disable time t oh sdo for maximum c l =30pf for minimum c l =8pf 15 - 50 ns scl to chip select t scc scl, ncs 15 - - ns ncs h pulse width t chw ncs 40 - - ns chip select setup time chip select hold time t css t csh ncs 60 6 5 - - - - ns note: the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. logic high and low levels are specified as 30% and 70% of iovcc for input signals. tf t f tr tr f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.144- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 8.4.3 rgb interface characteristics ( vssa=0v, iovcc=1.65v to 3.3v, vci=2.3v to 3.3v,t a = -30 to 70 c ) spec. item symbol condition min. typ. max. unit pixel low pulse width t clklt - 15 - - ns pixel high pulse width t clkht - 15 - - ns vertical sync. set-up time t vsst - 15 - - ns vertical sync. hold time t vssht - 15 - - ns horizontal sync. set-up time t hsst - 15 - - ns horizontal sync. hold time t vssht - 15 - - ns data enable set-up time t dest - 15 - - ns data enable hold time t deht - 15 - - ns data set-up time t dst - 15 - - ns data hold time t dht - 15 - - ns phase difference of sync signal falling edge thv - 0 - 240 dotclk note: the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. 3 tf t f tr tr vih vil t vsst thv vih vil t dst /t dest t dht /t deht t pclkcyc t hsht t hsst t vsht t pclkht t pclklt vih vil vsync hsync dotclk db[b:0] de f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.145- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 specification item symbol condition min typ. max unit vertical timing vertical cycle period t vp - 324 326 352 hs vertical low pulse width t vs - 2 2 - hs vertical front porch t vfp - 2 2 16 hs vertical back porch t vbp - 2 4 16 hs vertical blanking period t vbl t vbp + t vfp 4 6 32 hs - - hs - - hs vertical active area t vdisp - - 320 - hs vertical refresh rate tvrr frame rate 50 60 80 hz horizontal timing horizontal cycle period t hp - 244 252 272 dotclk horizontal low pulse width t hs - 2 2 - dotclk horizontal front porch t hfp - 2 4 16 dotclk horizontal back porch t hbp - 2 8 16 dotclk horizontal blanking period t hbl t hbp + t hfp 4 12 32 dotclk horizontal active area t hdisp - - 240 - dotclk pixel clock cycle tvrr=60hz f clkcyc - 3.9 - 10 mhz note: (1) iovcc=1.65 to 3.3v, vci=2.3 to 3.3v, vssa=vssd=0v, t a =-30 to 70 (to +85 no damage) (2) data lines can be set to high or low during blanking time C dont care. (3) hp is multiples of dotclk. f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.146- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 8.4.4 reset input timing figure 8.5: reset input timing spec. symbol parameter related pins min. typ. max. note unit tresw reset low pulse width (1) nreset 10 - - - s - - - 5 when reset applied during stb mode ms trest reset complete time (2) - - 120 when reset applied during stb mode ms tpres reset goes high level after power on time nreset & iovcc 1 - - reset goes high level after power on ms note: (1) spike due to an electrostatic discharge on nreset line does not cause irregular system reset according to the table below. (2) during the resetting period, the display will be blanked (the display is entering blanking sequence, which m aximum time is 120 ms, when reset starts in stb out Cmode. the display remains the blank state in stb Cmode) and then return to default condition for h/w reset. (3) during reset complete time, vmf value in otp will be latched to internal register during this period. this loading is done every time when there is h/w reset complete time (trest) within 5ms after a rising edge of nreset. (4) spike rejection also applies during a valid reset pulse as shown below: (5) it is necessary to wait 5msec after releasing !res before sending commands. also stb out nreset pulse action shorter than 5s reset rejected longer than 10s reset between 5 s and 10s reset start f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ -p.147- h imax confidential december, 2009 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. HX8347-B 240rgb x 320 dot, 262k color, tft mobile single chip driver data sheet preliminary v01 9. ordering information p art no. package HX8347-B000 pdxxx pd : mean cog xxx : mean chip thickness (m), (default: 280 m) 10.revision history version date d escription of changes 01 2009/12/24 new setup f o r ^xy?? o n l y http://www..net/ datasheet pdf - http://www..net/ |
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